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authorJacob Shin <jacob.w.shin@gmail.com>2006-06-26 13:58:47 +0200
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-26 10:48:20 -0700
commit17fc14ff1bdbc393e1cf4f6fd1e1e53d72ab9fe5 (patch)
tree9992a9079f4792f423f1e421d93814509b2c7d88 /arch
parentc38bfdc85aae0c6d1458269c0e063c2f4a116711 (diff)
downloadop-kernel-dev-17fc14ff1bdbc393e1cf4f6fd1e1e53d72ab9fe5.zip
op-kernel-dev-17fc14ff1bdbc393e1cf4f6fd1e1e53d72ab9fe5.tar.gz
[PATCH] x86_64: apic support for extended apic interrupt
Add support for extended APIC LVT found in future AMD processors. Signed-off-by: Jacob Shin <jacob.shin@amd.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86_64/kernel/apic.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c
index 53fc17d..396e125 100644
--- a/arch/x86_64/kernel/apic.c
+++ b/arch/x86_64/kernel/apic.c
@@ -909,15 +909,13 @@ int setup_profiling_timer(unsigned int multiplier)
return -EINVAL;
}
-#ifdef CONFIG_X86_MCE_AMD
-void setup_threshold_lvt(unsigned long lvt_off)
+void setup_APIC_extened_lvt(unsigned char lvt_off, unsigned char vector,
+ unsigned char msg_type, unsigned char mask)
{
- unsigned int v = 0;
- unsigned long reg = (lvt_off << 4) + 0x500;
- v |= THRESHOLD_APIC_VECTOR;
+ unsigned long reg = (lvt_off << 4) + K8_APIC_EXT_LVT_BASE;
+ unsigned int v = (mask << 16) | (msg_type << 8) | vector;
apic_write(reg, v);
}
-#endif /* CONFIG_X86_MCE_AMD */
#undef APIC_DIVISOR
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