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authorMax Filippov <jcmvbkbc@gmail.com>2014-02-07 11:09:52 +0400
committerMax Filippov <jcmvbkbc@gmail.com>2014-02-21 21:33:40 +0400
commit8e9356c6146d0bb81a6ffb02eae522e57ff29662 (patch)
treeb4c2ccc657fc0cf58354562683400b079a6d8702 /arch/xtensa
parente9d6dca51823b94e1ca28cb5e9180701d4375d61 (diff)
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op-kernel-dev-8e9356c6146d0bb81a6ffb02eae522e57ff29662.tar.gz
xtensa: fsf: drop nonexistent GPIO32 support
The toolchain for xtensa FSF core never supported GPIO32, drop it on the linux side too. Reported-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Baruch Siach <baruch@tkos.co.il>
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/Kconfig1
-rw-r--r--arch/xtensa/variants/fsf/include/variant/tie.h9
2 files changed, 2 insertions, 8 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index ba56e11..1cfb3d5 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -80,7 +80,6 @@ choice
config XTENSA_VARIANT_FSF
bool "fsf - default (not generic) configuration"
select MMU
- select HAVE_XTENSA_GPIO32
config XTENSA_VARIANT_DC232B
bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
diff --git a/arch/xtensa/variants/fsf/include/variant/tie.h b/arch/xtensa/variants/fsf/include/variant/tie.h
index bf40201..244cdea 100644
--- a/arch/xtensa/variants/fsf/include/variant/tie.h
+++ b/arch/xtensa/variants/fsf/include/variant/tie.h
@@ -18,13 +18,6 @@
#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
-/* Basic parameters of each coprocessor: */
-#define XCHAL_CP7_NAME "XTIOP"
-#define XCHAL_CP7_IDENT XTIOP
-#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
-#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
-#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
-
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_NCP_SA_SIZE 0
#define XCHAL_NCP_SA_ALIGN 1
@@ -42,6 +35,8 @@
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP6_SA_ALIGN 1
+#define XCHAL_CP7_SA_SIZE 0
+#define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 0
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