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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-03-02 20:12:54 -0800
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-03-02 20:12:54 -0800
commit17b02809cfa77abcab155ce3afbb1467e7f0744f (patch)
tree4bb7b08fa29e73fb29a8e56fec766643b1eaa82e /arch/xtensa/variants/fsf/include/variant/tie.h
parent9cd02bd876d3b1a5a93f0c9376f578bde03a6b26 (diff)
parent0414855fdc4a40da05221fc6062cccbc0c30f169 (diff)
downloadop-kernel-dev-17b02809cfa77abcab155ce3afbb1467e7f0744f.zip
op-kernel-dev-17b02809cfa77abcab155ce3afbb1467e7f0744f.tar.gz
Merge 3.14-rc5 into staging-next
We want those fixes in here
Diffstat (limited to 'arch/xtensa/variants/fsf/include/variant/tie.h')
-rw-r--r--arch/xtensa/variants/fsf/include/variant/tie.h9
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/xtensa/variants/fsf/include/variant/tie.h b/arch/xtensa/variants/fsf/include/variant/tie.h
index bf40201..244cdea 100644
--- a/arch/xtensa/variants/fsf/include/variant/tie.h
+++ b/arch/xtensa/variants/fsf/include/variant/tie.h
@@ -18,13 +18,6 @@
#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
-/* Basic parameters of each coprocessor: */
-#define XCHAL_CP7_NAME "XTIOP"
-#define XCHAL_CP7_IDENT XTIOP
-#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
-#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
-#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
-
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_NCP_SA_SIZE 0
#define XCHAL_NCP_SA_ALIGN 1
@@ -42,6 +35,8 @@
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP6_SA_ALIGN 1
+#define XCHAL_CP7_SA_SIZE 0
+#define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 0
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