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author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-10-05 17:44:48 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-10-05 17:44:48 -0700 |
commit | d8ea757b25ec82687c497fc90aa83f9bcea24b5b (patch) | |
tree | 4789c4d89f1ec77dcb27b855e2f479c3afd511cb /arch/xtensa/platforms/xt2000 | |
parent | 41844e36206be90cd4d962ea49b0abc3612a99d0 (diff) | |
parent | a4c6be5ad1d0c7af0c5421b68a00b6406b28a325 (diff) | |
download | op-kernel-dev-d8ea757b25ec82687c497fc90aa83f9bcea24b5b.zip op-kernel-dev-d8ea757b25ec82687c497fc90aa83f9bcea24b5b.tar.gz |
Merge tag 'xtensa-20161005' of git://github.com/jcmvbkbc/linux-xtensa
Pull Xtensa updates from Max Filippov:
"Updates for the xtensa architecture. It is a combined set of patches
for 4.8 that never got to the mainline and new patches for 4.9.
- add new kernel memory layouts for MMUv3 cores: with 256MB and 512MB
KSEG size, starting at physical address other than 0
- make kernel load address configurable
- clean up kernel memory layout macros
- drop sysmem early allocator and switch to memblock
- enable kmemleak and memory reservation from the device tree
- wire up new syscalls: userfaultfd, membarrier, mlock2,
copy_file_range, preadv2 and pwritev2
- add new platform: Cadence Configurable System Platform (CSP) and
new core variant for it: xt_lnx
- rearrange CCOUNT calibration code, make most of it generic
- improve machine reset code (XTFPGA now reboots reliably with MMUv3
cores)
- provide default memmap command line option for configurations
without device tree support
- ISS fixes: simdisk is now capable of using highmem pages, panic
correctly terminates simulator"
* tag 'xtensa-20161005' of git://github.com/jcmvbkbc/linux-xtensa: (24 commits)
xtensa: disable MMU initialization option on MMUv2 cores
xtensa: add default memmap and mmio32native options to defconfigs
xtensa: add default memmap option to common_defconfig
xtensa: add default memmap option to iss_defconfig
xtensa: ISS: allow simdisk to use high memory buffers
xtensa: ISS: define simc_exit and use it instead of inline asm
xtensa: xtfpga: group platform_* functions together
xtensa: rearrange CCOUNT calibration
xtensa: xtfpga: use clock provider, don't update DT
xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.
xtensa: initialize MMU before jumping to reset vector
xtensa: fix icountlevel setting in cpu_reset
xtensa: extract common CPU reset code into separate function
xtensa: Added Cadence CSP kernel configuration for Xtensa
xtensa: fix default kernel load address
xtensa: wire up new syscalls
xtensa: support reserved-memory DT node
xtensa: drop sysmem and switch to memblock
xtensa: minimize use of PLATFORM_DEFAULT_MEM_{ADDR,SIZE}
xtensa: cleanup MMU setup and kernel layout macros
...
Diffstat (limited to 'arch/xtensa/platforms/xt2000')
-rw-r--r-- | arch/xtensa/platforms/xt2000/setup.c | 21 |
1 files changed, 1 insertions, 20 deletions
diff --git a/arch/xtensa/platforms/xt2000/setup.c b/arch/xtensa/platforms/xt2000/setup.c index 4904c5c..9c2f1fb 100644 --- a/arch/xtensa/platforms/xt2000/setup.c +++ b/arch/xtensa/platforms/xt2000/setup.c @@ -64,26 +64,7 @@ void platform_restart(void) { /* Flush and reset the mmu, simulate a processor reset, and * jump to the reset vector. */ - - __asm__ __volatile__ ("movi a2, 15\n\t" - "wsr a2, icountlevel\n\t" - "movi a2, 0\n\t" - "wsr a2, icount\n\t" -#if XCHAL_NUM_IBREAK > 0 - "wsr a2, ibreakenable\n\t" -#endif -#if XCHAL_HAVE_LOOPS - "wsr a2, lcount\n\t" -#endif - "movi a2, 0x1f\n\t" - "wsr a2, ps\n\t" - "isync\n\t" - "jx %0\n\t" - : - : "a" (XCHAL_RESET_VECTOR_VADDR) - : "a2" - ); - + cpu_reset(); /* control never gets here */ } |