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| author | Baruch Siach <baruch@tkos.co.il> | 2013-12-29 11:03:30 +0200 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2014-01-15 00:25:14 +0400 |
| commit | 6cb971114f633a0bf240c20b681d989b45e3ec56 (patch) | |
| tree | 15d3280cf733e2bda26252e1c01b53943b47bd68 /arch/xtensa/mm | |
| parent | f8935f307fe46faa1a829a6b76ee95ca9ba67d20 (diff) | |
| download | op-kernel-dev-6cb971114f633a0bf240c20b681d989b45e3ec56.zip op-kernel-dev-6cb971114f633a0bf240c20b681d989b45e3ec56.tar.gz | |
xtensa: remap io area defined in device tree
Use the simple-bus node to discover the io area, and remap the cached and
bypass io ranges. The parent-bus-address value of the first triplet in the
"ranges" property is used. This value is rounded down to the nearest 256MB
boundary. The length of the io area is fixed at 256MB; the "ranges" property
length value is ignored.
Other limitations: (1) only the first simple-bus node is considered, and (2)
only the first triplet of the "ranges" property is considered.
See ePAPR 1.1 §6.5 for the simple-bus node description, and §2.3.8 for the
"ranges" property description.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/mm')
| -rw-r--r-- | arch/xtensa/mm/mmu.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/xtensa/mm/mmu.c b/arch/xtensa/mm/mmu.c index 5bb8e3c..36ec171 100644 --- a/arch/xtensa/mm/mmu.c +++ b/arch/xtensa/mm/mmu.c @@ -13,6 +13,8 @@ #include <asm/tlbflush.h> #include <asm/mmu_context.h> #include <asm/page.h> +#include <asm/initialize_mmu.h> +#include <asm/io.h> void __init paging_init(void) { @@ -37,6 +39,20 @@ void init_mmu(void) set_itlbcfg_register(0); set_dtlbcfg_register(0); #endif +#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF + /* + * Update the IO area mapping in case xtensa_kio_paddr has changed + */ + write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK), + XCHAL_KIO_CACHED_VADDR + 6); + write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK), + XCHAL_KIO_CACHED_VADDR + 6); + write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS), + XCHAL_KIO_BYPASS_VADDR + 6); + write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS), + XCHAL_KIO_BYPASS_VADDR + 6); +#endif + local_flush_tlb_all(); /* Set rasid register to a known value. */ |
