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| author | Max Filippov <jcmvbkbc@gmail.com> | 2016-03-07 01:36:33 +0300 |
|---|---|---|
| committer | Chris Zankel <chris@zankel.net> | 2016-03-11 08:53:32 +0000 |
| commit | 6ec7026ac01f3db039e0428db1f37590685ad3e7 (patch) | |
| tree | 9a3ac45e85c4ba604ce9dde4d14c103c9d2e70ff /arch/xtensa/include | |
| parent | 816aa58895ca4a6176caded477a655fc82aab5f5 (diff) | |
| download | op-kernel-dev-6ec7026ac01f3db039e0428db1f37590685ad3e7.zip op-kernel-dev-6ec7026ac01f3db039e0428db1f37590685ad3e7.tar.gz | |
xtensa: use context structure for debug exceptions
With implementation of data breakpoints debug exceptions raised when
PS.EXCM is set need to be handled, e.g. window overflow code can write
to watched userspace address. Currently debug exception handler uses
EXCSAVE and DEPC SRs to save temporary registers, but DEPC may not be
available when PS.EXCM is set and more space will be needed to save
additional state.
Reorganize debug context: create per-CPU structure debug_table instance
and store its address in the EXCSAVE<debug level> instead of
debug_exception function address. Expand this structure when more save
space is needed.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/include')
| -rw-r--r-- | arch/xtensa/include/asm/traps.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/traps.h index 28f33a8..3ad151a 100644 --- a/arch/xtensa/include/asm/traps.h +++ b/arch/xtensa/include/asm/traps.h @@ -65,4 +65,13 @@ static inline void spill_registers(void) #endif } +struct debug_table { + /* Pointer to debug exception handler */ + void (*debug_exception)(void); + /* Temporary register save area */ + unsigned long debug_save[1]; +}; + +void debug_exception(void); + #endif /* _XTENSA_TRAPS_H */ |
