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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-11-09 16:32:13 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-11-09 16:32:13 -0800 |
| commit | 3510ca19a82ba4c6a17af79c1f0448622a406efa (patch) | |
| tree | 79b9e734100e40f379e9b4c3c50d261c3cdc2fa8 /arch/xtensa/include/asm/initialize_mmu.h | |
| parent | e4da7e9a54649d6877ac23828ff93ce7191eae2c (diff) | |
| parent | afaa7c542cc9c4d8a99ba252a8ea5e8bc7c897e2 (diff) | |
| download | op-kernel-dev-3510ca19a82ba4c6a17af79c1f0448622a406efa.zip op-kernel-dev-3510ca19a82ba4c6a17af79c1f0448622a406efa.tar.gz | |
Merge tag 'xtensa-20151108' of git://github.com/czankel/xtensa-linux
Pull xtensa updates from Chris Zankel:
- fix remaining issues with noMMU cores
- fix build for cores w/o cache or zero overhead loop options
- fix boot of secondary cores in SMP configuration
- add support for DMA to high memory pages
- add dma_to_phys and phys_to_dma functions.
* tag 'xtensa-20151108' of git://github.com/czankel/xtensa-linux:
xtensa: implement dma_to_phys and phys_to_dma
xtensa: support DMA to high memory
Revert "xtensa: cache inquiry and unaligned cache handling functions"
xtensa: drop unused sections and remapped reset handlers
xtensa: fix secondary core boot in SMP
xtensa: add FORCE_MAX_ZONEORDER to Kconfig
xtensa: nommu: provide defconfig for de212 on kc705
xtensa: nommu: xtfpga: add kc705 DTS
xtensa: add de212 core variant
xtensa: nommu: select HAVE_FUTEX_CMPXCHG
xtensa: nommu: fix default memory start address
xtensa: nommu: provide correct KIO addresses
xtensa: nommu: fix USER_RING definition
xtensa: xtfpga: fix integer overflow in TASK_SIZE
xtensa: fix build for configs without cache options
xtensa: fixes for configs without loop option
Diffstat (limited to 'arch/xtensa/include/asm/initialize_mmu.h')
| -rw-r--r-- | arch/xtensa/include/asm/initialize_mmu.h | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h index e256f22..7a1e075 100644 --- a/arch/xtensa/include/asm/initialize_mmu.h +++ b/arch/xtensa/include/asm/initialize_mmu.h @@ -161,7 +161,8 @@ #endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY */ -#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS +#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \ + (XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE) /* Enable data and instruction cache in the DEFAULT_MEMORY region * if the processor has DTLB and ITLB. */ @@ -175,14 +176,18 @@ 1: sub a9, a9, a8 2: +#if XCHAL_DCACHE_SIZE rdtlb1 a3, a5 - ritlb1 a4, a5 and a3, a3, a6 - and a4, a4, a6 or a3, a3, a7 - or a4, a4, a7 wdtlb a3, a5 +#endif +#if XCHAL_ICACHE_SIZE + ritlb1 a4, a5 + and a4, a4, a6 + or a4, a4, a7 witlb a4, a5 +#endif add a5, a5, a8 bltu a8, a9, 1b |
