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| author | Andi Kleen <ak@suse.de> | 2006-01-11 22:42:02 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-11 19:01:09 -0800 |
| commit | 130951ccb14167c20b87e8bed52b60864ed53c2b (patch) | |
| tree | c54ee85b8f63d82007d1473a35b24fed3d5e2359 /arch/x86_64 | |
| parent | 2765130b020c22f803afba74772f33f2ad13bf28 (diff) | |
| download | op-kernel-dev-130951ccb14167c20b87e8bed52b60864ed53c2b.zip op-kernel-dev-130951ccb14167c20b87e8bed52b60864ed53c2b.tar.gz | |
[PATCH] x86_64: Support constant TSC feature in future AMD CPUs.
Based on the documentation recently posted by Richard Brunner.
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/x86_64')
| -rw-r--r-- | arch/x86_64/kernel/setup.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c index a0e0c9c..754a05f 100644 --- a/arch/x86_64/kernel/setup.c +++ b/arch/x86_64/kernel/setup.c @@ -910,6 +910,10 @@ static int __init init_amd(struct cpuinfo_x86 *c) } display_cacheinfo(c); + /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */ + if (c->x86_power & (1<<8)) + set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability); + if (c->extended_cpuid_level >= 0x80000008) { c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1; if (c->x86_max_cores & (c->x86_max_cores - 1)) @@ -1268,6 +1272,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) "ttp", /* thermal trip */ "tm", "stc" + "?", + "constant_tsc", }; |
