diff options
| author | Andi Kleen <ak@linux.intel.com> | 2011-10-12 17:46:34 -0700 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2011-10-14 13:16:38 +0200 |
| commit | 30963c0ac721f70aea0352ed1cd0fc3cfbaef730 (patch) | |
| tree | 8c39b11daee487a52b6745984e60156d6ff74e70 /arch/x86 | |
| parent | 506ed6b53e00ba303ad778122f08e1fca7cf5efb (diff) | |
| download | op-kernel-dev-30963c0ac721f70aea0352ed1cd0fc3cfbaef730.zip op-kernel-dev-30963c0ac721f70aea0352ed1cd0fc3cfbaef730.tar.gz | |
x86, intel: Use c->microcode for Atom errata check
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 26627a3..5231312 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -64,17 +64,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) * need the microcode to have already been loaded... so if it is * not, recommend a BIOS update and disable large pages. */ - if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) { - u32 ucode, junk; - - wrmsr(MSR_IA32_UCODE_REV, 0, 0); - sync_core(); - rdmsr(MSR_IA32_UCODE_REV, junk, ucode); - - if (ucode < 0x20e) { - printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n"); - clear_cpu_cap(c, X86_FEATURE_PSE); - } + if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 && + c->microcode < 0x20e) { + printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n"); + clear_cpu_cap(c, X86_FEATURE_PSE); } #ifdef CONFIG_X86_64 |
