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authorJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>2009-04-24 00:26:50 -0700
committerJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>2009-05-08 15:55:24 -0700
commita789ed5fb6d0256c4177c2cc27e06520ddbe4d4c (patch)
treeafdbb0c64c15ec522eae260949bfec02df2291b2 /arch/x86/xen
parentb80119bb35a49a4e8dbfb9708872adfd5cf38dee (diff)
downloadop-kernel-dev-a789ed5fb6d0256c4177c2cc27e06520ddbe4d4c.zip
op-kernel-dev-a789ed5fb6d0256c4177c2cc27e06520ddbe4d4c.tar.gz
xen: cache cr0 value to avoid trap'n'emulate for read_cr0
stts() is implemented in terms of read_cr0/write_cr0 to update the state of the TS bit. This happens during context switch, and so is fairly performance critical. Rather than falling back to a trap-and-emulate native read_cr0, implement our own by caching the last-written value from write_cr0 (the TS bit is the only one we really care about). Impact: optimise Xen context switches Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Diffstat (limited to 'arch/x86/xen')
-rw-r--r--arch/x86/xen/enlighten.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index e9df942..0a1700a 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -658,10 +658,26 @@ static void xen_clts(void)
xen_mc_issue(PARAVIRT_LAZY_CPU);
}
+static DEFINE_PER_CPU(unsigned long, xen_cr0_value);
+
+static unsigned long xen_read_cr0(void)
+{
+ unsigned long cr0 = percpu_read(xen_cr0_value);
+
+ if (unlikely(cr0 == 0)) {
+ cr0 = native_read_cr0();
+ percpu_write(xen_cr0_value, cr0);
+ }
+
+ return cr0;
+}
+
static void xen_write_cr0(unsigned long cr0)
{
struct multicall_space mcs;
+ percpu_write(xen_cr0_value, cr0);
+
/* Only pay attention to cr0.TS; everything else is
ignored. */
mcs = xen_mc_entry(0);
@@ -847,7 +863,7 @@ static const struct pv_cpu_ops xen_cpu_ops __initdata = {
.clts = xen_clts,
- .read_cr0 = native_read_cr0,
+ .read_cr0 = xen_read_cr0,
.write_cr0 = xen_write_cr0,
.read_cr4 = native_read_cr4,
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