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| author | Jacob Pan <jacob.jun.pan@linux.intel.com> | 2010-07-16 11:58:26 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2010-07-16 16:52:15 -0700 |
| commit | f82c3d71d6fd2e6a3e3416f09099e29087e39abf (patch) | |
| tree | 2101f7be744320cce3356e290fb4ba6c1796a1c2 /arch/x86/pci | |
| parent | fd19dce7ac07973f700b0f13fb7f94b951414a4c (diff) | |
| download | op-kernel-dev-f82c3d71d6fd2e6a3e3416f09099e29087e39abf.zip op-kernel-dev-f82c3d71d6fd2e6a3e3416f09099e29087e39abf.tar.gz | |
x86, pci, mrst: Add extra sanity check in walking the PCI extended cap chain
The fixed bar capability structure is searched in PCI extended
configuration space. We need to make sure there is a valid capability
ID to begin with otherwise, the search code may stuck in a infinite
loop which results in boot hang. This patch adds additional check for
cap ID 0, which is also invalid, and indicates end of chain.
End of chain is supposed to have all fields zero, but that doesn't
seem to always be the case in the field.
Suggested-by: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
LKML-Reference: <1279306706-27087-1-git-send-email-jacob.jun.pan@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/pci')
| -rw-r--r-- | arch/x86/pci/mrst.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c index 7ef3a27..cb29191 100644 --- a/arch/x86/pci/mrst.c +++ b/arch/x86/pci/mrst.c @@ -66,8 +66,9 @@ static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn) devfn, pos, 4, &pcie_cap)) return 0; - if (pcie_cap == 0xffffffff) - return 0; + if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 || + PCI_EXT_CAP_ID(pcie_cap) == 0xffff) + break; if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) { raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, @@ -76,7 +77,7 @@ static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn) return pos; } - pos = pcie_cap >> 20; + pos = PCI_EXT_CAP_NEXT(pcie_cap); } return 0; |
