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authorRobert Richter <robert.richter@amd.com>2008-08-22 20:23:37 +0200
committerIngo Molnar <mingo@elte.hu>2008-08-23 17:39:30 +0200
commit9b4e27b52853c5da77e61a4e36fbc40688b7a829 (patch)
tree83cae2da59bf5fe1b3f5cb5dc0f08a0cdb8fe63c /arch/x86/pci
parent9754a5b840a209bc1f192d59f63e81b698a55ac8 (diff)
downloadop-kernel-dev-9b4e27b52853c5da77e61a4e36fbc40688b7a829.zip
op-kernel-dev-9b4e27b52853c5da77e61a4e36fbc40688b7a829.tar.gz
x86: fix: do not run code in amd_bus.c on non-AMD CPUs
Jan Beulich wrote: > Even worse - this would even try to access the MSR on non-AMD CPUs > (currently probably prevented just by the fact that only AMD ones use > family values of 0x10 or higher). This patch adds cpu vendor check to the postcore_initcalls. Reported-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/pci')
-rw-r--r--arch/x86/pci/amd_bus.c19
1 files changed, 16 insertions, 3 deletions
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index dbf5323..4a6f1a6 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -555,9 +555,11 @@ static int __init early_fill_mp_bus_info(void)
return 0;
}
-postcore_initcall(early_fill_mp_bus_info);
+#else /* !CONFIG_X86_64 */
-#endif
+static int __init early_fill_mp_bus_info(void) { return 0; }
+
+#endif /* !CONFIG_X86_64 */
/* common 32/64 bit code */
@@ -583,4 +585,15 @@ static int __init enable_pci_io_ecs(void)
return 0;
}
-postcore_initcall(enable_pci_io_ecs);
+static int __init amd_postcore_init(void)
+{
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+ return 0;
+
+ early_fill_mp_bus_info();
+ enable_pci_io_ecs();
+
+ return 0;
+}
+
+postcore_initcall(amd_postcore_init);
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