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| author | Junaid Shahid <junaids@google.com> | 2016-12-06 16:46:15 -0800 |
|---|---|---|
| committer | Radim Krčmář <rkrcmar@redhat.com> | 2017-01-09 14:46:10 +0100 |
| commit | 37f0e8fe6b10ee2ab52576caa721ee1282de74a6 (patch) | |
| tree | 586978d589093bfb1bbd2200f64b3e51d1c66402 /arch/x86/kvm | |
| parent | f39a058d0ea2f58b9c69cfcf7c93184f33302c98 (diff) | |
| download | op-kernel-dev-37f0e8fe6b10ee2ab52576caa721ee1282de74a6.zip op-kernel-dev-37f0e8fe6b10ee2ab52576caa721ee1282de74a6.tar.gz | |
kvm: x86: mmu: Do not use bit 63 for tracking special SPTEs
MMIO SPTEs currently set both bits 62 and 63 to distinguish them as special
PTEs. However, bit 63 is used as the SVE bit in Intel EPT PTEs. The SVE bit
is ignored for misconfigured PTEs but not necessarily for not-Present PTEs.
Since MMIO SPTEs use an EPT misconfiguration, so using bit 63 for them is
acceptable. However, the upcoming fast access tracking feature adds another
type of special tracking PTE, which uses not-Present PTEs and hence should
not set bit 63.
In order to use common bits to distinguish both type of special PTEs, we
now use only bit 62 as the special bit.
Signed-off-by: Junaid Shahid <junaids@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm')
| -rw-r--r-- | arch/x86/kvm/vmx.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 81159a3..6f53ded 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -5236,10 +5236,10 @@ static void ept_set_mmio_spte_mask(void) /* * EPT Misconfigurations can be generated if the value of bits 2:0 * of an EPT paging-structure entry is 110b (write/execute). - * Also, magic bits (0x3ull << 62) is set to quickly identify mmio - * spte. + * Also, special bit (62) is set to quickly identify mmio spte. */ - kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull); + kvm_mmu_set_mmio_spte_mask(SPTE_SPECIAL_MASK | + VMX_EPT_MISCONFIG_WX_VALUE); } #define VMX_XSS_EXIT_BITMAP 0 |
