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authorMichael S. Tsirkin <mst@redhat.com>2014-05-07 16:29:48 +0300
committerPaolo Bonzini <pbonzini@redhat.com>2014-05-07 18:00:49 +0200
commitb63cf42fd1d8c18fab71222321aaf356f63089c9 (patch)
tree6a2f42a81adb0895f6b823c87a8b62700d2f7d82 /arch/x86/kvm/svm.c
parent5f7dde7bbb3c628766676cbd63c0a1834035d6fa (diff)
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kvm/x86: implement hv EOI assist
It seems that it's easy to implement the EOI assist on top of the PV EOI feature: simply convert the page address to the format expected by PV EOI. Notes: -"No EOI required" is set only if interrupt injected is edge triggered; this is true because level interrupts are going through IOAPIC which disables PV EOI. In any case, if guest triggers EOI the bit will get cleared on exit. -For migration, set of HV_X64_MSR_APIC_ASSIST_PAGE sets KVM_PV_EOI_EN internally, so restoring HV_X64_MSR_APIC_ASSIST_PAGE seems sufficient In any case, bit is cleared on exit so worst case it's never re-enabled -no handling of PV EOI data is performed at HV_X64_MSR_EOI write; HV_X64_MSR_EOI is a separate optimization - it's an X2APIC replacement that lets you do EOI with an MSR and not IO. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm/svm.c')
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