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| author | Peter Zijlstra <peterz@infradead.org> | 2013-09-12 12:53:44 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2013-09-12 19:13:37 +0200 |
| commit | 2b9e344df384e595db24ac61ae5f780e9b024878 (patch) | |
| tree | 8fdbf56c0a5f2700a104f546ac1871382cf45e0c /arch/x86/kernel/cpu/perf_event.h | |
| parent | 4b2c4f1f1b71fe18381f089c501ac21cd2167dfa (diff) | |
| download | op-kernel-dev-2b9e344df384e595db24ac61ae5f780e9b024878.zip op-kernel-dev-2b9e344df384e595db24ac61ae5f780e9b024878.tar.gz | |
perf/x86/intel: Clean up checkpoint-interrupt bits
Clean up the weird CP interrupt exception code by keeping a CP mask.
Andi suggested this implementation but weirdly didn't actually
implement it himself, do so now because it removes the conditional in
the interrupt handler and avoids the assumption its only on cnt2.
Suggested-by: Andi Kleen <andi@firstfloor.org>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/n/tip-dvb4q0rydkfp00kqat4p5bah@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_event.h')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h index cc16faa..ce84ede 100644 --- a/arch/x86/kernel/cpu/perf_event.h +++ b/arch/x86/kernel/cpu/perf_event.h @@ -164,6 +164,11 @@ struct cpu_hw_events { struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; /* + * Intel checkpoint mask + */ + u64 intel_cp_status; + + /* * manage shared (per-core, per-cpu) registers * used on Intel NHM/WSM/SNB */ |
