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author | Andreas Schwab <schwab@suse.de> | 2009-01-27 21:45:57 +0100 |
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committer | Ingo Molnar <mingo@elte.hu> | 2009-01-30 23:55:25 +0100 |
commit | 7fc49f19813030f2e15ad2ccec5cb701f7f4a3ec (patch) | |
tree | b4e52b975777e18151811019541e24f0a6f2bfc8 /arch/x86/kernel/cpu/intel_cacheinfo.c | |
parent | 618b2c8db24522ae273d8299c6a936ea13793c4d (diff) | |
download | op-kernel-dev-7fc49f19813030f2e15ad2ccec5cb701f7f4a3ec.zip op-kernel-dev-7fc49f19813030f2e15ad2ccec5cb701f7f4a3ec.tar.gz |
x86 setup: fix asm constraints in vesa_store_edid
Impact: fix potential miscompile (currently believed non-manifest)
As the comment explains, the VBE DDC call can clobber any register.
Tell the compiler about that fact.
Signed-off-by: Andreas Schwab <schwab@suse.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/intel_cacheinfo.c')
0 files changed, 0 insertions, 0 deletions