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| author | Thomas Gleixner <tglx@linutronix.de> | 2018-05-10 20:31:44 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-05-17 17:09:19 +0200 |
| commit | 0270be3e34efb05a88bc4c422572ece038ef3608 (patch) | |
| tree | 6cde6ccb097a4c516f2d58d3583943a16b449ecd /arch/x86/kernel/cpu/bugs.c | |
| parent | 11fb0683493b2da112cd64c9dada221b52463bf7 (diff) | |
| download | op-kernel-dev-0270be3e34efb05a88bc4c422572ece038ef3608.zip op-kernel-dev-0270be3e34efb05a88bc4c422572ece038ef3608.tar.gz | |
x86/speculation: Rework speculative_store_bypass_update()
The upcoming support for the virtual SPEC_CTRL MSR on AMD needs to reuse
speculative_store_bypass_update() to avoid code duplication. Add an
argument for supplying a thread info (TIF) value and create a wrapper
speculative_store_bypass_update_current() which is used at the existing
call site.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Diffstat (limited to 'arch/x86/kernel/cpu/bugs.c')
| -rw-r--r-- | arch/x86/kernel/cpu/bugs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 82422a0..f2f0c1b 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -598,7 +598,7 @@ static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) * mitigation until it is next scheduled. */ if (task == current && update) - speculative_store_bypass_update(); + speculative_store_bypass_update_current(); return 0; } |
