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authorCyrill Gorcunov <gorcunov@gmail.com>2008-08-18 20:45:54 +0400
committerIngo Molnar <mingo@elte.hu>2008-08-19 02:07:15 +0200
commitc43da2f5e92fe3bcc256f0c0d6cb858368da5bd9 (patch)
treeb58c1716b6758a25d96cfa933cdc5da2369f6c95 /arch/x86/kernel/apic_32.c
parent36c9d6742897fa414f51c4e9d0f20ab4e6bf942c (diff)
downloadop-kernel-dev-c43da2f5e92fe3bcc256f0c0d6cb858368da5bd9.zip
op-kernel-dev-c43da2f5e92fe3bcc256f0c0d6cb858368da5bd9.tar.gz
x86: apic - unify lapic_setup_esr
We use 32bit code former for 64bit mode since it's much better implementation and easier to merge. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/apic_32.c')
-rw-r--r--arch/x86/kernel/apic_32.c21
1 files changed, 11 insertions, 10 deletions
diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c
index 6d230e9..3c1562a 100644
--- a/arch/x86/kernel/apic_32.c
+++ b/arch/x86/kernel/apic_32.c
@@ -983,6 +983,16 @@ static void __cpuinit lapic_setup_esr(void)
{
unsigned long oldvalue, value, maxlvt;
if (lapic_is_integrated() && !esr_disable) {
+ if (esr_disable) {
+ /*
+ * Something untraceable is creating bad interrupts on
+ * secondary quads ... for the moment, just leave the
+ * ESR disabled - we can't do anything useful with the
+ * errors anyway - mbligh
+ */
+ printk(KERN_INFO "Leaving ESR disabled.\n");
+ return;
+ }
/* !82489DX */
maxlvt = lapic_get_maxlvt();
if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
@@ -1003,16 +1013,7 @@ static void __cpuinit lapic_setup_esr(void)
"vector: 0x%08lx after: 0x%08lx\n",
oldvalue, value);
} else {
- if (esr_disable)
- /*
- * Something untraceable is creating bad interrupts on
- * secondary quads ... for the moment, just leave the
- * ESR disabled - we can't do anything useful with the
- * errors anyway - mbligh
- */
- printk(KERN_INFO "Leaving ESR disabled.\n");
- else
- printk(KERN_INFO "No ESR for 82489DX.\n");
+ printk(KERN_INFO "No ESR for 82489DX.\n");
}
}
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