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authorRobert Richter <robert.richter@amd.com>2011-12-15 17:56:39 +0100
committerIngo Molnar <mingo@elte.hu>2012-03-08 11:35:22 +0100
commitdb98c5faf8cb350212ea3af786cb3ba0d4e7a01e (patch)
treededbbe76714b416b5e6d62d30b8488a9c0f6c1c2 /arch/x86/include
parent4db2e8e6500d9ba6406f2714fa3968b39a325274 (diff)
downloadop-kernel-dev-db98c5faf8cb350212ea3af786cb3ba0d4e7a01e.zip
op-kernel-dev-db98c5faf8cb350212ea3af786cb3ba0d4e7a01e.tar.gz
perf/x86: Implement 64-bit counter support for IBS
This patch implements 64 bit counter support for IBS. The sampling period is no longer limited to the hw counter width. The functions perf_event_set_period() and perf_event_try_update() can be used as generic functions. They can replace similar code that is duplicate across architectures. Signed-off-by: Robert Richter <robert.richter@amd.com> Acked-by: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Link: http://lkml.kernel.org/r/1323968199-9326-5-git-send-email-robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/perf_event.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index e8fb2c7..9cf6696 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -177,6 +177,8 @@ struct x86_pmu_capability {
#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
/* IbsOpCtl bits */
+/* lower 4 bits of the current count are ignored: */
+#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
#define IBS_OP_CNT_CTL (1ULL<<19)
#define IBS_OP_VAL (1ULL<<18)
#define IBS_OP_ENABLE (1ULL<<17)
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