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| author | Boris Ostrovsky <boris.ostrovsky@amd.com> | 2013-01-29 16:32:49 -0500 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2013-01-31 13:35:38 -0800 |
| commit | f0322bd341fd63261527bf84afd3272bcc2e8dd3 (patch) | |
| tree | 40138ddb8827ab5945c8d13b5ae731bc92018443 /arch/x86/include/uapi/asm/msr-index.h | |
| parent | 6bf08a8dcd1ef13e542f08fc3b1ce6cf64ae63b6 (diff) | |
| download | op-kernel-dev-f0322bd341fd63261527bf84afd3272bcc2e8dd3.zip op-kernel-dev-f0322bd341fd63261527bf84afd3272bcc2e8dd3.tar.gz | |
x86, AMD: Enable WC+ memory type on family 10 processors
In some cases BIOS may not enable WC+ memory type on family 10
processors, instead converting what would be WC+ memory to CD type.
On guests using nested pages this could result in performance
degradation. This patch enables WC+.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
Link: http://lkml.kernel.org/r/1359495169-23278-1-git-send-email-ostr@amd64.org
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/include/uapi/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index 433a59f..158cde9 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -173,6 +173,7 @@ #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 #define MSR_AMD64_DC_CFG 0xc0011022 +#define MSR_AMD64_BU_CFG2 0xc001102a #define MSR_AMD64_IBSFETCHCTL 0xc0011030 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 |
