diff options
| author | Robert Richter <robert.richter@amd.com> | 2010-10-06 12:27:54 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-10-20 04:42:13 +0200 |
| commit | 27afdf2008da0b8878a73e32e4eb12381b84e224 (patch) | |
| tree | 84aaf8c200f597553a2874b30d9589718d937878 /arch/x86/include/asm | |
| parent | a68c439b1966c91f0ef474e2bf275d6792312726 (diff) | |
| download | op-kernel-dev-27afdf2008da0b8878a73e32e4eb12381b84e224.zip op-kernel-dev-27afdf2008da0b8878a73e32e4eb12381b84e224.tar.gz | |
apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets
We want the BIOS to setup the EILVT APIC registers. The offsets
were hardcoded and BIOS settings were overwritten by the OS.
Now, the subsystems for MCE threshold and IBS determine the LVT
offset from the registers the BIOS has setup. If the BIOS setup
is buggy on a family 10h system, a workaround enables IBS. If
the OS determines an invalid register setup, a "[Firmware Bug]:
" error message is reported.
We need this change also for upcomming cpu families.
Signed-off-by: Robert Richter <robert.richter@amd.com>
LKML-Reference: <1286360874-1471-3-git-send-email-robert.richter@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm')
| -rw-r--r-- | arch/x86/include/asm/apic.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 1fa03e0..286de34 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -252,9 +252,7 @@ static inline int apic_is_clustered_box(void) } #endif -extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); -extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); - +extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); #else /* !CONFIG_X86_LOCAL_APIC */ static inline void lapic_shutdown(void) { } |
