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authorvenkatesh.pallipadi@intel.com <venkatesh.pallipadi@intel.com>2008-12-18 11:41:31 -0800
committerH. Peter Anvin <hpa@zytor.com>2008-12-18 13:30:16 -0800
commit8a7b12f70fb135a1b1d865687de3edcdc780f6d1 (patch)
tree149ceb1d8aba6a46e90513275cfdd090c847cc48 /arch/x86/include/asm/pgtable_32.h
parent5899329b19100c0b82dc78e9b21ed8b920c9ffb3 (diff)
downloadop-kernel-dev-8a7b12f70fb135a1b1d865687de3edcdc780f6d1.zip
op-kernel-dev-8a7b12f70fb135a1b1d865687de3edcdc780f6d1.tar.gz
x86: PAT: change pgprot_noncached to uc_minus instead of strong uc - v3
Impact: mm behavior change. Make pgprot_noncached uc_minus instead of strong UC. This will make pgprot_noncached to be in line with ioremap_nocache() and all the other APIs that map page uc_minus on uc request. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/pgtable_32.h')
-rw-r--r--arch/x86/include/asm/pgtable_32.h9
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h
index f9d5889..72b020d 100644
--- a/arch/x86/include/asm/pgtable_32.h
+++ b/arch/x86/include/asm/pgtable_32.h
@@ -101,15 +101,6 @@ extern unsigned long pg0[];
#endif
/*
- * Macro to mark a page protection value as "uncacheable".
- * On processors which do not support it, this is a no-op.
- */
-#define pgprot_noncached(prot) \
- ((boot_cpu_data.x86 > 3) \
- ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) \
- : (prot))
-
-/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
*/
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