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authorIngo Molnar <mingo@elte.hu>2009-01-28 05:01:41 +0100
committerIngo Molnar <mingo@elte.hu>2009-01-28 23:20:17 +0100
commitf6f52baf2613dd319e9ba3f3319bf1f1c442e4b3 (patch)
tree1eb8f814939501c10f3f18af86f9c5a5d25c7310 /arch/x86/include/asm/mach-default
parentfe402e1f2b67a63f1e53ab2a316fc20f7ca4ec91 (diff)
downloadop-kernel-dev-f6f52baf2613dd319e9ba3f3319bf1f1c442e4b3.zip
op-kernel-dev-f6f52baf2613dd319e9ba3f3319bf1f1c442e4b3.tar.gz
x86: clean up esr_disable() methods
Impact: cleanup Most subarchitectures want to disable the APIC ESR (Error Status Register), because they generally have hardware hacks that wrap standard CPUs into a bigger system and hence the APIC bus is quite non-standard and weirdnesses (lockups) have been seen with ESR reporting. Remove the esr_disable macros and put the desired flag into each subarchitecture's genapic template directly. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/mach-default')
-rw-r--r--arch/x86/include/asm/mach-default/mach_apic.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/x86/include/asm/mach-default/mach_apic.h b/arch/x86/include/asm/mach-default/mach_apic.h
index 77a9724..5f8d17fd 100644
--- a/arch/x86/include/asm/mach-default/mach_apic.h
+++ b/arch/x86/include/asm/mach-default/mach_apic.h
@@ -18,7 +18,6 @@ static inline const struct cpumask *default_target_cpus(void)
}
#define NO_BALANCE_IRQ (0)
-#define esr_disable (0)
#ifdef CONFIG_X86_64
#include <asm/genapic.h>
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