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authorIngo Molnar <mingo@elte.hu>2008-12-16 20:59:24 +0100
committerIngo Molnar <mingo@elte.hu>2008-12-16 21:01:15 +0100
commitd4377974062122d6d9be0bbd8a910a0954714194 (patch)
treea044b2e54325a43ec6e762c02ff53e0297b0bd2e /arch/x86/include/asm/cpufeature.h
parentdd7a5230cd651bfb119d222561c4032f30dd5659 (diff)
downloadop-kernel-dev-d4377974062122d6d9be0bbd8a910a0954714194.zip
op-kernel-dev-d4377974062122d6d9be0bbd8a910a0954714194.tar.gz
x86: support always running TSC on Intel CPUs, add cpufeature definition
Impact: add new synthetic-cpuid bit definition add X86_FEATURE_NONSTOP_TSC to the cpufeature bits - this is in preparation of Venki's always-running-TSC patch. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/cpufeature.h')
-rw-r--r--arch/x86/include/asm/cpufeature.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 5bce8ed..ea408dc 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -92,6 +92,7 @@
#define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */
#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */
#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
+#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
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