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authorAlex Shi <alex.shi@intel.com>2012-03-03 19:27:27 +0800
committerIngo Molnar <mingo@elte.hu>2012-03-05 09:19:20 +0100
commit901b04450a0ff44d579158b8b0492ce7e66cd442 (patch)
tree4db8e537f71b0bbae9c0fcf065335156ec967bde /arch/x86/Kconfig.cpu
parente24b90b282d73c0654c716d449d91a07ebb8ecaf (diff)
downloadop-kernel-dev-901b04450a0ff44d579158b8b0492ce7e66cd442.zip
op-kernel-dev-901b04450a0ff44d579158b8b0492ce7e66cd442.tar.gz
x86/numa: Improve internode cache alignment
Currently cache alignment among nodes in the kernel is still 128 bytes on x86 NUMA machines - we got that X86_INTERNODE_CACHE_SHIFT default from old P4 processors. But now most modern x86 CPUs use the same size: 64 bytes from L1 to last level L3. so let's remove the incorrect setting, and directly use the L1 cache size to do SMP cache line alignment. This patch saves some memory space on kernel data, and it also improves the cache locality of kernel data. The System.map is quite different with/without this change: before patch after patch ... 000000000000b000 d tlb_vector_| 000000000000b000 d tlb_vector 000000000000b080 d cpu_loops_p| 000000000000b040 d cpu_loops_ ... Signed-off-by: Alex Shi <alex.shi@intel.com> Cc: asit.k.mallick@intel.com Link: http://lkml.kernel.org/r/1330774047-18597-1-git-send-email-alex.shi@intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/Kconfig.cpu')
-rw-r--r--arch/x86/Kconfig.cpu1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 3c57033..6443c6f 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -303,7 +303,6 @@ config X86_GENERIC
config X86_INTERNODE_CACHE_SHIFT
int
default "12" if X86_VSMP
- default "7" if NUMA
default X86_L1_CACHE_SHIFT
config X86_CMPXCHG
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