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authorThierry Reding <thierry.reding@avionic-design.de>2012-09-14 16:14:25 +0800
committerThierry Reding <thierry.reding@avionic-design.de>2012-10-05 20:56:39 +0200
commitd1b6886502160eb771aefe21c1f891597138ddfe (patch)
treeeee4f1aade9c3b34878ba849301a196532a9fdd0 /arch/unicore32/include
parent60ce70285b4d3b933eea15e494a9b35fe85b19b7 (diff)
downloadop-kernel-dev-d1b6886502160eb771aefe21c1f891597138ddfe.zip
op-kernel-dev-d1b6886502160eb771aefe21c1f891597138ddfe.tar.gz
unicore32: pwm: Properly remap memory-mapped registers
Instead of writing to the timer controller registers by dereferencing a pointer to the memory location, properly remap the memory region with a call to ioremap_nocache() and access the registers using writel(). Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Tested-by: Qin Rui <qinrui@mprc.pku.edu.cn>
Diffstat (limited to 'arch/unicore32/include')
-rw-r--r--arch/unicore32/include/mach/regs-ost.h18
1 files changed, 8 insertions, 10 deletions
diff --git a/arch/unicore32/include/mach/regs-ost.h b/arch/unicore32/include/mach/regs-ost.h
index 7b91fe6..4a85fb4 100644
--- a/arch/unicore32/include/mach/regs-ost.h
+++ b/arch/unicore32/include/mach/regs-ost.h
@@ -33,18 +33,16 @@
* Interrupt Enable Reg OST_OIER
*/
#define OST_OIER (PKUNITY_OST_BASE + 0x001C)
+
/*
- * PWM Pulse Width Control Reg OST_PWMPWCR
- */
-#define OST_PWMPWCR (PKUNITY_OST_BASE + 0x0080)
-/*
- * PWM Duty Cycle Control Reg OST_PWMDCCR
- */
-#define OST_PWMDCCR (PKUNITY_OST_BASE + 0x0084)
-/*
- * PWM Period Control Reg OST_PWMPCR
+ * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80
+ * PWCR: Pulse Width Control Reg
+ * DCCR: Duty Cycle Control Reg
+ * PCR: Period Control Reg
*/
-#define OST_PWMPCR (PKUNITY_OST_BASE + 0x0088)
+#define OST_PWM_PWCR (0x00)
+#define OST_PWM_DCCR (0x04)
+#define OST_PWM_PCR (0x08)
/*
* Match detected 0 OST_OSSR_M0
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