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author | GuanXuetao <gxt@mprc.pku.edu.cn> | 2011-02-26 20:08:36 +0800 |
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committer | GuanXuetao <gxt@mprc.pku.edu.cn> | 2011-03-17 09:19:14 +0800 |
commit | b08b4f8e63e60a64f81e194269be14afee396f33 (patch) | |
tree | d76aef05929a7f28f1463c72adefd8af780192c8 /arch/unicore32/include/mach/regs-spi.h | |
parent | fa7499ef77db8d535e3c609c8064e9ee50c0693c (diff) | |
download | op-kernel-dev-b08b4f8e63e60a64f81e194269be14afee396f33.zip op-kernel-dev-b08b4f8e63e60a64f81e194269be14afee396f33.tar.gz |
unicore32 machine related files: hardware registers
This patch adds all hardware registers definitions.
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Diffstat (limited to 'arch/unicore32/include/mach/regs-spi.h')
-rw-r--r-- | arch/unicore32/include/mach/regs-spi.h | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/arch/unicore32/include/mach/regs-spi.h b/arch/unicore32/include/mach/regs-spi.h new file mode 100644 index 0000000..cadc713 --- /dev/null +++ b/arch/unicore32/include/mach/regs-spi.h @@ -0,0 +1,98 @@ +/* + * PKUnity Serial Peripheral Interface (SPI) Registers + */ +/* + * Control reg. 0 SPI_CR0 + */ +#define SPI_CR0 __REG(PKUNITY_SPI_BASE + 0x0000) +/* + * Control reg. 1 SPI_CR1 + */ +#define SPI_CR1 __REG(PKUNITY_SPI_BASE + 0x0004) +/* + * Enable reg SPI_SSIENR + */ +#define SPI_SSIENR __REG(PKUNITY_SPI_BASE + 0x0008) +/* + * Status reg SPI_SR + */ +#define SPI_SR __REG(PKUNITY_SPI_BASE + 0x0028) +/* + * Interrupt Mask reg SPI_IMR + */ +#define SPI_IMR __REG(PKUNITY_SPI_BASE + 0x002C) +/* + * Interrupt Status reg SPI_ISR + */ +#define SPI_ISR __REG(PKUNITY_SPI_BASE + 0x0030) + +/* + * Enable SPI Controller SPI_SSIENR_EN + */ +#define SPI_SSIENR_EN FIELD(1, 1, 0) + +/* + * SPI Busy SPI_SR_BUSY + */ +#define SPI_SR_BUSY FIELD(1, 1, 0) +/* + * Transmit FIFO Not Full SPI_SR_TFNF + */ +#define SPI_SR_TFNF FIELD(1, 1, 1) +/* + * Transmit FIFO Empty SPI_SR_TFE + */ +#define SPI_SR_TFE FIELD(1, 1, 2) +/* + * Receive FIFO Not Empty SPI_SR_RFNE + */ +#define SPI_SR_RFNE FIELD(1, 1, 3) +/* + * Receive FIFO Full SPI_SR_RFF + */ +#define SPI_SR_RFF FIELD(1, 1, 4) + +/* + * Trans. FIFO Empty Interrupt Status SPI_ISR_TXEIS + */ +#define SPI_ISR_TXEIS FIELD(1, 1, 0) +/* + * Trans. FIFO Overflow Interrupt Status SPI_ISR_TXOIS + */ +#define SPI_ISR_TXOIS FIELD(1, 1, 1) +/* + * Receiv. FIFO Underflow Interrupt Status SPI_ISR_RXUIS + */ +#define SPI_ISR_RXUIS FIELD(1, 1, 2) +/* + * Receiv. FIFO Overflow Interrupt Status SPI_ISR_RXOIS + */ +#define SPI_ISR_RXOIS FIELD(1, 1, 3) +/* + * Receiv. FIFO Full Interrupt Status SPI_ISR_RXFIS + */ +#define SPI_ISR_RXFIS FIELD(1, 1, 4) +#define SPI_ISR_MSTIS FIELD(1, 1, 5) + +/* + * Trans. FIFO Empty Interrupt Mask SPI_IMR_TXEIM + */ +#define SPI_IMR_TXEIM FIELD(1, 1, 0) +/* + * Trans. FIFO Overflow Interrupt Mask SPI_IMR_TXOIM + */ +#define SPI_IMR_TXOIM FIELD(1, 1, 1) +/* + * Receiv. FIFO Underflow Interrupt Mask SPI_IMR_RXUIM + */ +#define SPI_IMR_RXUIM FIELD(1, 1, 2) +/* + * Receiv. FIFO Overflow Interrupt Mask SPI_IMR_RXOIM + */ +#define SPI_IMR_RXOIM FIELD(1, 1, 3) +/* + * Receiv. FIFO Full Interrupt Mask SPI_IMR_RXFIM + */ +#define SPI_IMR_RXFIM FIELD(1, 1, 4) +#define SPI_IMR_MSTIM FIELD(1, 1, 5) + |