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author | Maciej W. Rozycki <macro@linux-mips.org> | 2015-04-03 23:26:49 +0100 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-08 01:10:05 +0200 |
commit | 2d83fea786d7aeb5b3b76bd492d9b3bccc0f823c (patch) | |
tree | ff3ca66d494d9b367aeefa99f07b70aa5eeb72e7 /arch/um | |
parent | 80cbfad790962125b542cb0cb637954c04386b30 (diff) | |
download | op-kernel-dev-2d83fea786d7aeb5b3b76bd492d9b3bccc0f823c.zip op-kernel-dev-2d83fea786d7aeb5b3b76bd492d9b3bccc0f823c.tar.gz |
MIPS: Correct FP ISA requirements
Correct ISA requirements for floating-point instructions:
* the CU3 exception signifies a real COP3 instruction in MIPS I & II,
* the BC1FL and BC1TL instructions are not supported in MIPS I,
* the SQRT.fmt instructions are indeed supported in MIPS II,
* the LDC1 and SDC1 instructions are indeed supported in MIPS32r1,
* the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions
are indeed supported in MIPS32,
* the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in
MIPS32r2 and MIPS32r6,
* the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions
are indeed supported in MIPS32r2 and MIPS32r6,
* the RSQRT.fmt and RECIP.fmt instructions are indeed supported in
MIPS64r1,
Also simplify conditionals for MIPS III and MIPS IV FPU instructions and
the handling of the MOVCI minor opcode.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9700/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/um')
0 files changed, 0 insertions, 0 deletions