summaryrefslogtreecommitdiffstats
path: root/arch/um/os-Linux/time.c
diff options
context:
space:
mode:
authorAlistair Popple <alistair@popple.id.au>2018-04-17 19:11:28 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2018-04-24 09:46:57 +1000
commitd0cf9b561ca97d5245bb9e0c4774b7fadd897d67 (patch)
tree4b991ef6e71000ab4f70fe6cce1096f6e32a3b90 /arch/um/os-Linux/time.c
parenta1409adac748f0db655e096521bbe6904aadeb98 (diff)
downloadop-kernel-dev-d0cf9b561ca97d5245bb9e0c4774b7fadd897d67.zip
op-kernel-dev-d0cf9b561ca97d5245bb9e0c4774b7fadd897d67.tar.gz
powerpc/powernv/npu: Do a PID GPU TLB flush when invalidating a large address range
The NPU has a limited number of address translation shootdown (ATSD) registers and the GPU has limited bandwidth to process ATSDs. This can result in contention of ATSD registers leading to soft lockups on some threads, particularly when invalidating a large address range in pnv_npu2_mn_invalidate_range(). At some threshold it becomes more efficient to flush the entire GPU TLB for the given MM context (PID) than individually flushing each address in the range. This patch will result in ranges greater than 2MB being converted from 32+ ATSDs into a single ATSD which will flush the TLB for the given PID on each GPU. Fixes: 1ab66d1fbada ("powerpc/powernv: Introduce address translation services for Nvlink2") Cc: stable@vger.kernel.org # v4.12+ Signed-off-by: Alistair Popple <alistair@popple.id.au> Acked-by: Balbir Singh <bsingharora@gmail.com> Tested-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/um/os-Linux/time.c')
0 files changed, 0 insertions, 0 deletions
OpenPOWER on IntegriCloud