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authorYijing Wang <wangyijing@huawei.com>2013-09-09 21:13:04 +0800
committerBjorn Helgaas <bhelgaas@google.com>2013-09-24 12:10:04 -0600
commit503275bf371fbab01a14f2e9fd1ac7aa20c81645 (patch)
tree295daeca82f990fce2400440234526af6b1bb264 /arch/tile
parentf1c66c4678ad223bda0dcd261e4048f009234f85 (diff)
downloadop-kernel-dev-503275bf371fbab01a14f2e9fd1ac7aa20c81645.zip
op-kernel-dev-503275bf371fbab01a14f2e9fd1ac7aa20c81645.tar.gz
tile/PCI: use cached pci_dev->pcie_mpss to simplify code
The PCI core caches the "PCIe Max Payload Size Supported" in pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword(). Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'arch/tile')
-rw-r--r--arch/tile/kernel/pci.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index b7180e6..c45593d 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -251,15 +251,12 @@ static void fixup_read_and_payload_sizes(void)
/* Scan for the smallest maximum payload size. */
for_each_pci_dev(dev) {
u32 devcap;
- int max_payload;
if (!pci_is_pcie(dev))
continue;
- pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap);
- max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
- if (max_payload < smallest_max_payload)
- smallest_max_payload = max_payload;
+ if (dev->pcie_mpss < smallest_max_payload)
+ smallest_max_payload = dev->pcie_mpss;
}
/* Now, set the max_payload_size for all devices to that value. */
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