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authorChris Metcalf <cmetcalf@tilera.com>2012-03-29 15:25:59 -0400
committerChris Metcalf <cmetcalf@tilera.com>2012-05-25 12:48:24 -0400
commitcd6f32aa088f4d328e676c35f51b440f2fe5b98c (patch)
tree5668ff37a8690e5f5d919992756edb4466c37de2 /arch/tile/kernel
parentd5d14ed6f2db7287a5088e1350cf422bf72140b3 (diff)
downloadop-kernel-dev-cd6f32aa088f4d328e676c35f51b440f2fe5b98c.zip
op-kernel-dev-cd6f32aa088f4d328e676c35f51b440f2fe5b98c.tar.gz
arch/tile: support <asm/cachectl.h> header for cacheflush() syscall
We already had a syscall that did some dcache flushing, but it was not used in practice. Make it MIPS compatible instead so it can do both the DCACHE and ICACHE actions. We have code that wants to be able to use the ICACHE flush mode from userspace so this change enables that. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/kernel')
-rw-r--r--arch/tile/kernel/sys.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/tile/kernel/sys.c b/arch/tile/kernel/sys.c
index cb44ba7..b08095b 100644
--- a/arch/tile/kernel/sys.c
+++ b/arch/tile/kernel/sys.c
@@ -32,11 +32,17 @@
#include <asm/syscalls.h>
#include <asm/pgtable.h>
#include <asm/homecache.h>
+#include <asm/cachectl.h>
#include <arch/chip.h>
-SYSCALL_DEFINE0(flush_cache)
+SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len,
+ unsigned long, flags)
{
- homecache_evict(cpumask_of(smp_processor_id()));
+ if (flags & DCACHE)
+ homecache_evict(cpumask_of(smp_processor_id()));
+ if (flags & ICACHE)
+ flush_remote(0, HV_FLUSH_EVICT_L1I, mm_cpumask(current->mm),
+ 0, 0, 0, NULL, NULL, 0);
return 0;
}
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