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| author | Chris Metcalf <cmetcalf@tilera.com> | 2010-11-01 15:24:29 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2010-11-01 15:30:42 -0400 |
| commit | 5d966115de84c22cd4df029cb00be0e51fab6c10 (patch) | |
| tree | 85095d93900f7f76a7591620651c5480065cacfb /arch/tile/kernel/setup.c | |
| parent | 38a6f4266989c4dae68eccb1a5cb4580a48003e4 (diff) | |
| download | op-kernel-dev-5d966115de84c22cd4df029cb00be0e51fab6c10.zip op-kernel-dev-5d966115de84c22cd4df029cb00be0e51fab6c10.tar.gz | |
arch/tile: bomb raw_local_irq_ to arch_local_irq_
This completes the tile migration to the new naming scheme for
the architecture-specific irq management code.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/kernel/setup.c')
| -rw-r--r-- | arch/tile/kernel/setup.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c index ae51cad..fb0b3cb 100644 --- a/arch/tile/kernel/setup.c +++ b/arch/tile/kernel/setup.c @@ -868,14 +868,14 @@ void __cpuinit setup_cpu(int boot) /* Allow asynchronous TLB interrupts. */ #if CHIP_HAS_TILE_DMA() - raw_local_irq_unmask(INT_DMATLB_MISS); - raw_local_irq_unmask(INT_DMATLB_ACCESS); + arch_local_irq_unmask(INT_DMATLB_MISS); + arch_local_irq_unmask(INT_DMATLB_ACCESS); #endif #if CHIP_HAS_SN_PROC() - raw_local_irq_unmask(INT_SNITLB_MISS); + arch_local_irq_unmask(INT_SNITLB_MISS); #endif #ifdef __tilegx__ - raw_local_irq_unmask(INT_SINGLE_STEP_K); + arch_local_irq_unmask(INT_SINGLE_STEP_K); #endif /* |
