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authorPalmer Dabbelt <palmer@dabbelt.com>2017-08-02 14:44:50 -0500
committerBjorn Helgaas <bhelgaas@google.com>2017-08-02 14:53:16 -0500
commitecf677c8dcaa7bf13eee31b4d9e4639d559984ad (patch)
treef831c3251c69bd7b0cb49fecc549ab56846927fd /arch/tile/kernel/pci_gx.c
parentbccf90d6e063d278b9ddc78dd266d0adef29886c (diff)
downloadop-kernel-dev-ecf677c8dcaa7bf13eee31b4d9e4639d559984ad.zip
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PCI: Add a generic weak pcibios_align_resource()
Multiple architectures define this as a trivial function, and I'm adding another one as part of the RISC-V port. Add a __weak version of pcibios_align_resource() and delete the now-obselete ones in a handful of ports. The only functional change should be that a handful of ports used to export pcibios_fixup_bus(). Only some architectures export this, so I just dropped it. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'arch/tile/kernel/pci_gx.c')
-rw-r--r--arch/tile/kernel/pci_gx.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c
index b89172b..0a76421 100644
--- a/arch/tile/kernel/pci_gx.c
+++ b/arch/tile/kernel/pci_gx.c
@@ -108,15 +108,6 @@ static struct pci_ops tile_cfg_ops;
/* Mask of CPUs that should receive PCIe interrupts. */
static struct cpumask intr_cpus_map;
-/* We don't need to worry about the alignment of resources. */
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
- resource_size_t size,
- resource_size_t align)
-{
- return res->start;
-}
-EXPORT_SYMBOL(pcibios_align_resource);
-
/*
* Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
* For now, we simply send interrupts to non-dataplane CPUs.
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