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| author | Chris Metcalf <cmetcalf@tilera.com> | 2013-08-10 12:35:02 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2013-08-30 11:56:58 -0400 |
| commit | 35f059761c5ac313d13372fe3cdaa41bce3d0dbf (patch) | |
| tree | 1a8f7e0eba01afac74c081348530fccd63dc48e4 /arch/tile/kernel/head_64.S | |
| parent | 4036c7d3542ce82ea343bf95dd05ca46aefba9aa (diff) | |
| download | op-kernel-dev-35f059761c5ac313d13372fe3cdaa41bce3d0dbf.zip op-kernel-dev-35f059761c5ac313d13372fe3cdaa41bce3d0dbf.tar.gz | |
tilegx: change how we find the kernel stack
Previously, we used a special-purpose register (SPR_SYSTEM_SAVE_K_0)
to hold the CPU number and the top of the current kernel stack
by using the low bits to hold the CPU number, and using the high
bits to hold the address of the page just above where we'd want
the kernel stack to be. That way we could initialize a new SP
when first entering the kernel by just masking the SPR value and
subtracting a couple of words.
However, it's actually more useful to be able to place an arbitrary
kernel-top value in the SPR. This allows us to create a new stack
context (e.g. for virtualization) with an arbitrary top-of-stack VA.
To make this work, we now store the CPU number in the high bits,
above the highest legal VA bit (42 bits in the current tilegx
microarchitecture). The full 42 bits are thus available to store the
top of stack value. Getting the current cpu (a relatively common
operation) is still fast; it's now a shift rather than a mask.
We make this change only for tilegx, since tilepro has too few SPR
bits to do this, and we don't need this support on tilepro anyway.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/kernel/head_64.S')
| -rw-r--r-- | arch/tile/kernel/head_64.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/tile/kernel/head_64.S b/arch/tile/kernel/head_64.S index 969e4f8..652b814 100644 --- a/arch/tile/kernel/head_64.S +++ b/arch/tile/kernel/head_64.S @@ -158,7 +158,7 @@ ENTRY(_start) /* * Load up our per-cpu offset. When the first (master) tile * boots, this value is still zero, so we will load boot_pc - * with start_kernel, and boot_sp with init_stack + THREAD_SIZE. + * with start_kernel, and boot_sp with at the top of init_stack. * The master tile initializes the per-cpu offset array, so that * when subsequent (secondary) tiles boot, they will instead load * from their per-cpu versions of boot_sp and boot_pc. @@ -202,9 +202,9 @@ ENTRY(_start) } ld r0, r0 ld sp, r1 - or r4, sp, r4 + shli r4, r4, CPU_SHIFT + bfins r4, sp, 0, CPU_SHIFT-1 mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */ - addi sp, sp, -STACK_TOP_DELTA { move lr, zero /* stop backtraces in the called function */ jr r0 |
