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author | David Woodhouse <David.Woodhouse@intel.com> | 2012-11-21 10:38:13 +0000 |
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committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-11-21 10:38:13 +0000 |
commit | 851462444d421c223965b12b836bef63da61b57f (patch) | |
tree | 495baa14e638817941496c36e1443aed7dae0ea0 /arch/tile/include/uapi/asm/cachectl.h | |
parent | 5a6ea4af0907f995dc06df21a9c9ef764c7cd3bc (diff) | |
parent | 6924d99fcdf1a688538a3cdebd1f135c22eec191 (diff) | |
download | op-kernel-dev-851462444d421c223965b12b836bef63da61b57f.zip op-kernel-dev-851462444d421c223965b12b836bef63da61b57f.tar.gz |
Merge branch 'for-3.7' of git://git.infradead.org/users/dedekind/l2-mtd
Conflicts:
drivers/mtd/nand/nand_base.c
Diffstat (limited to 'arch/tile/include/uapi/asm/cachectl.h')
-rw-r--r-- | arch/tile/include/uapi/asm/cachectl.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/tile/include/uapi/asm/cachectl.h b/arch/tile/include/uapi/asm/cachectl.h new file mode 100644 index 0000000..af4c9f9 --- /dev/null +++ b/arch/tile/include/uapi/asm/cachectl.h @@ -0,0 +1,42 @@ +/* + * Copyright 2011 Tilera Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for + * more details. + */ + +#ifndef _ASM_TILE_CACHECTL_H +#define _ASM_TILE_CACHECTL_H + +/* + * Options for cacheflush system call. + * + * The ICACHE flush is performed on all cores currently running the + * current process's address space. The intent is for user + * applications to be able to modify code, invoke the system call, + * then allow arbitrary other threads in the same address space to see + * the newly-modified code. Passing a length of CHIP_L1I_CACHE_SIZE() + * or more invalidates the entire icache on all cores in the address + * spaces. (Note: currently this option invalidates the entire icache + * regardless of the requested address and length, but we may choose + * to honor the arguments at some point.) + * + * Flush and invalidation of memory can normally be performed with the + * __insn_flush(), __insn_inv(), and __insn_finv() instructions from + * userspace. The DCACHE option to the system call allows userspace + * to flush the entire L1+L2 data cache from the core. In this case, + * the address and length arguments are not used. The DCACHE flush is + * restricted to the current core, not all cores in the address space. + */ +#define ICACHE (1<<0) /* invalidate L1 instruction cache */ +#define DCACHE (1<<1) /* flush and invalidate data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +#endif /* _ASM_TILE_CACHECTL_H */ |