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| author | Chris Metcalf <cmetcalf@tilera.com> | 2012-06-13 14:46:40 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2012-07-18 16:40:05 -0400 |
| commit | bbaa22c3a0d0be4406d26e5a73d1e8e504787986 (patch) | |
| tree | 4d00f1bda85d9735c60d7db1cdbdd215d5317ae4 /arch/tile/include/asm/Kbuild | |
| parent | 3e219b91533058e242b78ac08aaa91024dd6f369 (diff) | |
| download | op-kernel-dev-bbaa22c3a0d0be4406d26e5a73d1e8e504787986.zip op-kernel-dev-bbaa22c3a0d0be4406d26e5a73d1e8e504787986.tar.gz | |
tilegx pci: support I/O to arbitrarily-cached pages
The tilegx PCI root complex support (currently only in linux-next)
is limited to pages that are homed on cached in the default manner,
i.e. "hash-for-home". This change supports delivery of I/O data to
pages that are cached in other ways (locally on a particular core,
uncached, user-managed incoherent, etc.).
A large part of the change is supporting flushing pages from cache
on particular homes so that we can transition the data that we are
delivering to or from the device appropriately. The new homecache_finv*
routines handle this.
Some changes to page_table_range_init() were also required to make
the fixmap code work correctly on tilegx; it hadn't been used there
before.
We also remove some stub mark_caches_evicted_*() routines that
were just no-ops anyway.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/asm/Kbuild')
0 files changed, 0 insertions, 0 deletions
