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authorLinus Torvalds <torvalds@linux-foundation.org>2010-01-05 16:01:58 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2010-01-05 16:01:58 -0800
commiteb1c838fca2248ae62e5472b496ab52d3d774cc5 (patch)
treedc1e70881e0048fc67131f009e25a1aaece60901 /arch/sparc/kernel/perf_event.c
parentdb677ffa5f5a4f15b9dad4d132b3477b80766d82 (diff)
parente04ed38d4e0cd32141f723560efcc8252b0241e2 (diff)
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6: sparc64: Fix Niagara2 perf event handling. sparc64: Fix NMI programming when perf events are active. bbc_envctrl: Clean up properly if kthread_run() fails.
Diffstat (limited to 'arch/sparc/kernel/perf_event.c')
-rw-r--r--arch/sparc/kernel/perf_event.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index fa5936e..198fb4e 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -986,6 +986,17 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
data.addr = 0;
cpuc = &__get_cpu_var(cpu_hw_events);
+
+ /* If the PMU has the TOE IRQ enable bits, we need to do a
+ * dummy write to the %pcr to clear the overflow bits and thus
+ * the interrupt.
+ *
+ * Do this before we peek at the counters to determine
+ * overflow so we don't lose any events.
+ */
+ if (sparc_pmu->irq_bit)
+ pcr_ops->write(cpuc->pcr);
+
for (idx = 0; idx < MAX_HWEVENTS; idx++) {
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;
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