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authorIngo Molnar <mingo@elte.hu>2009-11-15 09:50:38 +0100
committerIngo Molnar <mingo@elte.hu>2009-11-15 09:50:41 +0100
commit39dc78b6510323848e3356452f7dab9499736978 (patch)
treecf8a8fede74e41b203fd00e3ccd21ead2e851442 /arch/sparc/include/asm/system_64.h
parent4c49b12853fbb5eff4849b7b6a1e895776f027a1 (diff)
parent156171c71a0dc4bce12b4408bb1591f8fe32dc1a (diff)
downloadop-kernel-dev-39dc78b6510323848e3356452f7dab9499736978.zip
op-kernel-dev-39dc78b6510323848e3356452f7dab9499736978.tar.gz
Merge commit 'v2.6.32-rc7' into perf/core
Merge reason: pick up perf fixlets Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/sparc/include/asm/system_64.h')
-rw-r--r--arch/sparc/include/asm/system_64.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h
index 25e848f..d47a98e 100644
--- a/arch/sparc/include/asm/system_64.h
+++ b/arch/sparc/include/asm/system_64.h
@@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
: : : "memory"); \
} while (0)
+/* The kernel always executes in TSO memory model these days,
+ * and furthermore most sparc64 chips implement more stringent
+ * memory ordering than required by the specifications.
+ */
#define mb() membar_safe("#StoreLoad")
#define rmb() __asm__ __volatile__("":::"memory")
#define wmb() __asm__ __volatile__("":::"memory")
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