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authorPaul Mundt <lethal@linux-sh.org>2012-01-12 13:11:43 +0900
committerPaul Mundt <lethal@linux-sh.org>2012-01-12 13:11:43 +0900
commitb1bdd255661369cb6eb90b6e181169b5e6d0f9b6 (patch)
tree17d15f3a6dc5bdd6205070dbef0e339421b13d25 /arch/sh
parent9d14070f656addddce3d63fd483de46930b51850 (diff)
parentc1537b4863da620f12f5b42ece61bf65314148ed (diff)
downloadop-kernel-dev-b1bdd255661369cb6eb90b6e181169b5e6d0f9b6.zip
op-kernel-dev-b1bdd255661369cb6eb90b6e181169b5e6d0f9b6.tar.gz
Merge branch 'sh/nommu' into sh-latest
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/Kconfig4
-rw-r--r--arch/sh/drivers/pci/pci.c23
-rw-r--r--arch/sh/mm/cache-sh2a.c123
3 files changed, 85 insertions, 65 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 47a2f1c..3c8db65 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -85,9 +85,6 @@ config GENERIC_GPIO
config GENERIC_CALIBRATE_DELAY
bool
-config GENERIC_IOMAP
- bool
-
config GENERIC_CLOCKEVENTS
def_bool y
@@ -861,6 +858,7 @@ config PCI
bool "PCI support"
depends on SYS_SUPPORTS_PCI
select PCI_DOMAINS
+ select GENERIC_PCI_IOMAP
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index c2691af..11aaf2f 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -393,29 +393,6 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
return (void __iomem *)(chan->io_map_base + port);
}
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
- resource_size_t start = pci_resource_start(dev, bar);
- resource_size_t len = pci_resource_len(dev, bar);
- unsigned long flags = pci_resource_flags(dev, bar);
-
- if (unlikely(!len || !start))
- return NULL;
- if (maxlen && len > maxlen)
- len = maxlen;
-
- if (flags & IORESOURCE_IO)
- return ioport_map_pci(dev, start, len);
- if (flags & IORESOURCE_MEM) {
- if (flags & IORESOURCE_CACHEABLE)
- return ioremap(start, len);
- return ioremap_nocache(start, len);
- }
-
- return NULL;
-}
-EXPORT_SYMBOL(pci_iomap);
-
void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
{
iounmap(addr);
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
index 1f51225..ae08cbb 100644
--- a/arch/sh/mm/cache-sh2a.c
+++ b/arch/sh/mm/cache-sh2a.c
@@ -15,35 +15,78 @@
#include <asm/cacheflush.h>
#include <asm/io.h>
+/*
+ * The maximum number of pages we support up to when doing ranged dcache
+ * flushing. Anything exceeding this will simply flush the dcache in its
+ * entirety.
+ */
+#define MAX_OCACHE_PAGES 32
+#define MAX_ICACHE_PAGES 32
+
+static void sh2a_flush_oc_line(unsigned long v, int way)
+{
+ unsigned long addr = (v & 0x000007f0) | (way << 11);
+ unsigned long data;
+
+ data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr);
+ if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+ data &= ~SH_CACHE_UPDATED;
+ __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr);
+ }
+}
+
+static void sh2a_invalidate_line(unsigned long cache_addr, unsigned long v)
+{
+ /* Set associative bit to hit all ways */
+ unsigned long addr = (v & 0x000007f0) | SH_CACHE_ASSOC;
+ __raw_writel((addr & CACHE_PHYSADDR_MASK), cache_addr | addr);
+}
+
+/*
+ * Write back the dirty D-caches, but not invalidate them.
+ */
static void sh2a__flush_wback_region(void *start, int size)
{
+#ifdef CONFIG_CACHE_WRITEBACK
unsigned long v;
unsigned long begin, end;
unsigned long flags;
+ int nr_ways;
begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
+ nr_ways = current_cpu_data.dcache.ways;
local_irq_save(flags);
jump_to_uncached();
- for (v = begin; v < end; v+=L1_CACHE_BYTES) {
- unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0);
+ /* If there are too many pages then flush the entire cache */
+ if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
+ begin = CACHE_OC_ADDRESS_ARRAY;
+ end = begin + (nr_ways * current_cpu_data.dcache.way_size);
+
+ for (v = begin; v < end; v += L1_CACHE_BYTES) {
+ unsigned long data = __raw_readl(v);
+ if (data & SH_CACHE_UPDATED)
+ __raw_writel(data & ~SH_CACHE_UPDATED, v);
+ }
+ } else {
int way;
- for (way = 0; way < 4; way++) {
- unsigned long data = __raw_readl(addr | (way << 11));
- if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
- data &= ~SH_CACHE_UPDATED;
- __raw_writel(data, addr | (way << 11));
- }
+ for (way = 0; way < nr_ways; way++) {
+ for (v = begin; v < end; v += L1_CACHE_BYTES)
+ sh2a_flush_oc_line(v, way);
}
}
back_to_cached();
local_irq_restore(flags);
+#endif
}
+/*
+ * Write back the dirty D-caches and invalidate them.
+ */
static void sh2a__flush_purge_region(void *start, int size)
{
unsigned long v;
@@ -58,13 +101,22 @@ static void sh2a__flush_purge_region(void *start, int size)
jump_to_uncached();
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
- __raw_writel((v & CACHE_PHYSADDR_MASK),
- CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
+#ifdef CONFIG_CACHE_WRITEBACK
+ int way;
+ int nr_ways = current_cpu_data.dcache.ways;
+ for (way = 0; way < nr_ways; way++)
+ sh2a_flush_oc_line(v, way);
+#endif
+ sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
}
+
back_to_cached();
local_irq_restore(flags);
}
+/*
+ * Invalidate the D-caches, but no write back please
+ */
static void sh2a__flush_invalidate_region(void *start, int size)
{
unsigned long v;
@@ -74,29 +126,25 @@ static void sh2a__flush_invalidate_region(void *start, int size)
begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
+
local_irq_save(flags);
jump_to_uncached();
-#ifdef CONFIG_CACHE_WRITEBACK
- __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
- /* I-cache invalidate */
- for (v = begin; v < end; v+=L1_CACHE_BYTES) {
- __raw_writel((v & CACHE_PHYSADDR_MASK),
- CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
- }
-#else
- for (v = begin; v < end; v+=L1_CACHE_BYTES) {
- __raw_writel((v & CACHE_PHYSADDR_MASK),
- CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
- __raw_writel((v & CACHE_PHYSADDR_MASK),
- CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
+ /* If there are too many pages then just blow the cache */
+ if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
+ __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
+ } else {
+ for (v = begin; v < end; v += L1_CACHE_BYTES)
+ sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
}
-#endif
+
back_to_cached();
local_irq_restore(flags);
}
-/* WBack O-Cache and flush I-Cache */
+/*
+ * Write back the range of D-cache, and purge the I-cache.
+ */
static void sh2a_flush_icache_range(void *args)
{
struct flusher_data *data = args;
@@ -107,23 +155,20 @@ static void sh2a_flush_icache_range(void *args)
start = data->addr1 & ~(L1_CACHE_BYTES-1);
end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
+#ifdef CONFIG_CACHE_WRITEBACK
+ sh2a__flush_wback_region((void *)start, end-start);
+#endif
+
local_irq_save(flags);
jump_to_uncached();
- for (v = start; v < end; v+=L1_CACHE_BYTES) {
- unsigned long addr = (v & 0x000007f0);
- int way;
- /* O-Cache writeback */
- for (way = 0; way < 4; way++) {
- unsigned long data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
- if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
- data &= ~SH_CACHE_UPDATED;
- __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
- }
- }
- /* I-Cache invalidate */
- __raw_writel(addr,
- CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
+ /* I-Cache invalidate */
+ /* If there are too many pages then just blow the cache */
+ if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
+ __raw_writel(__raw_readl(CCR) | CCR_ICACHE_INVALIDATE, CCR);
+ } else {
+ for (v = start; v < end; v += L1_CACHE_BYTES)
+ sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
}
back_to_cached();
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