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authorVince Weaver <vincent.weaver@maine.edu>2014-06-15 02:06:15 -0400
committerIngo Molnar <mingo@kernel.org>2014-06-19 19:37:51 +0200
commita10d60c08cc3bbea9195e2b36440f557373623eb (patch)
tree890b0d6fefaeda11289270d43bede967120d1d64 /arch/sh
parent97b1198fece06d495270222bcf5fde4c8cb0b5b0 (diff)
downloadop-kernel-dev-a10d60c08cc3bbea9195e2b36440f557373623eb.zip
op-kernel-dev-a10d60c08cc3bbea9195e2b36440f557373623eb.tar.gz
sh, perf: Use common PMU interrupt disabled code
Transition to using the new generic PERF_PMU_CAP_NO_INTERRUPT method for failing a sampling event when no PMU interrupt is available. Signed-off-by: Vince Weaver <vincent.weaver@maine.edu> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Paul Mackerras <paulus@samba.org> Cc: linux-sh@vger.kernel.org Link: http://lkml.kernel.org/r/alpine.DEB.2.10.1406150205300.16738@vincent-weaver-1.umelst.maine.edu Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/kernel/perf_event.c15
1 files changed, 7 insertions, 8 deletions
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index 0233167..7cfd7f1 100644
--- a/arch/sh/kernel/perf_event.c
+++ b/arch/sh/kernel/perf_event.c
@@ -129,14 +129,6 @@ static int __hw_perf_event_init(struct perf_event *event)
return -ENODEV;
/*
- * All of the on-chip counters are "limited", in that they have
- * no interrupts, and are therefore unable to do sampling without
- * further work and timer assistance.
- */
- if (hwc->sample_period)
- return -EINVAL;
-
- /*
* See if we need to reserve the counter.
*
* If no events are currently in use, then we have to take a
@@ -392,6 +384,13 @@ int register_sh_pmu(struct sh_pmu *_pmu)
pr_info("Performance Events: %s support registered\n", _pmu->name);
+ /*
+ * All of the on-chip counters are "limited", in that they have
+ * no interrupts, and are therefore unable to do sampling without
+ * further work and timer assistance.
+ */
+ pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
+
WARN_ON(_pmu->num_events > MAX_HWEVENTS);
perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
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