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authorMatt Fleming <matt@console-pimps.org>2009-10-06 21:22:25 +0000
committerPaul Mundt <lethal@linux-sh.org>2009-10-10 21:51:12 +0900
commit1f69b6af9171f50135cce8023c84d82fbf42a8f5 (patch)
tree8d664d2d24f6f199e0b3af0afe18c85969a902fd /arch/sh/mm
parent8bd642b17bea31f8361b61c16c8d154638414df4 (diff)
downloadop-kernel-dev-1f69b6af9171f50135cce8023c84d82fbf42a8f5.zip
op-kernel-dev-1f69b6af9171f50135cce8023c84d82fbf42a8f5.tar.gz
sh: Prepare for dynamic PMB support
To allow the MMU to be switched between 29bit and 32bit mode at runtime some constants need to swapped for functions that return a runtime value. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm')
-rw-r--r--arch/sh/mm/cache-sh4.c6
-rw-r--r--arch/sh/mm/init.c8
2 files changed, 11 insertions, 3 deletions
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 639bb32..56dd55a 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -88,12 +88,12 @@ static inline void flush_cache_4096(unsigned long start,
unsigned long flags, exec_offset = 0;
/*
- * All types of SH-4 require PC to be in P2 to operate on the I-cache.
- * Some types of SH-4 require PC to be in P2 to operate on the D-cache.
+ * All types of SH-4 require PC to be uncached to operate on the I-cache.
+ * Some types of SH-4 require PC to be uncached to operate on the D-cache.
*/
if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
(start < CACHE_OC_ADDRESS_ARRAY))
- exec_offset = 0x20000000;
+ exec_offset = cached_to_uncached;
local_irq_save(flags);
__flush_cache_4096(start | SH_CACHE_ASSOC,
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 8173e38..c8af6c5 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -323,4 +323,12 @@ int memory_add_physaddr_to_nid(u64 addr)
}
EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
#endif
+
#endif /* CONFIG_MEMORY_HOTPLUG */
+
+#ifdef CONFIG_PMB
+int __in_29bit_mode(void)
+{
+ return !(ctrl_inl(PMB_PASCR) & PASCR_SE);
+}
+#endif /* CONFIG_PMB */
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