diff options
| author | Arnd Hannemann <arnd@arndnet.de> | 2010-12-28 22:22:34 +0000 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2011-01-12 14:36:33 +0900 |
| commit | a68a07841848a25fa04918b441667fd192cea108 (patch) | |
| tree | 11a2262c7f77c56681dafa3153788b220990ea73 /arch/sh/kernel/cpu/sh4a/setup-sh7724.c | |
| parent | 4162cf64973df51fc885825bc9ca4d055891c49f (diff) | |
| download | op-kernel-dev-a68a07841848a25fa04918b441667fd192cea108.zip op-kernel-dev-a68a07841848a25fa04918b441667fd192cea108.tar.gz | |
sh: sh7724 Enable SDIO IRQs
This patch enables the interrupt generation for SDIO IRQs
of the sdhi controllers of the SoC. To make sure interrupt
are handled announce the MMC_CAP_SDIO_IRQ capability
on ecovec, kfr2r09 and se7724.
Tested with a b43-based SDIO wireless card on ecovec.
Signed-off-by: Arnd Hannemann <arnd@arndnet.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7724.c')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7724.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 828c965..c598a7f 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -1144,7 +1144,7 @@ static struct intc_group groups[] __initdata = { static struct intc_mask_reg mask_registers[] __initdata = { { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, - 0, DISABLED, ENABLED, ENABLED } }, + 0, ENABLED, ENABLED, ENABLED } }, { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, @@ -1166,7 +1166,7 @@ static struct intc_mask_reg mask_registers[] __initdata = { { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ - { DISABLED, DISABLED, ENABLED, ENABLED, + { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, SCIFA5, FSI } }, { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, |
