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| author | Arnd Hannemann <arnd@arndnet.de> | 2010-12-28 22:22:36 +0000 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2011-01-12 14:36:41 +0900 |
| commit | 365e108739a4b2b207bd61e066aa6eb9bd1b03c4 (patch) | |
| tree | 0521a3b04222624b6bf28910acafb348266bb28d /arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |
| parent | 464495e5d8ba58ce6c103a2a176abaf313c0c704 (diff) | |
| download | op-kernel-dev-365e108739a4b2b207bd61e066aa6eb9bd1b03c4.zip op-kernel-dev-365e108739a4b2b207bd61e066aa6eb9bd1b03c4.tar.gz | |
sh: sh7723 / ap325rxa enable SDIO IRQs
This patch enables the interrupt generation for SDIO IRQs
of the sdhi controllers of the SoC. To make sure SDIO IRQs
are used announce the MMC_CAP_SDIO_IRQ capability
on ap325rxa.
Signed-off-by: Arnd Hannemann <arnd@arndnet.de>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7723.c')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7723.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index 0eadefd..d764122 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c @@ -719,7 +719,7 @@ static struct intc_group groups[] __initdata = { static struct intc_mask_reg mask_registers[] __initdata = { { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, - 0, DISABLED, ENABLED, ENABLED } }, + 0, ENABLED, ENABLED, ENABLED } }, { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ @@ -736,7 +736,7 @@ static struct intc_mask_reg mask_registers[] __initdata = { { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ - { 0, DISABLED, ENABLED, ENABLED, + { 0, ENABLED, ENABLED, ENABLED, 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, |
