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author | Paul Mundt <lethal@linux-sh.org> | 2012-05-18 18:13:27 +0900 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2012-05-18 18:13:27 +0900 |
commit | c1dbccc3c7cc70e8211a7ad6ba55ecbc18e77a5a (patch) | |
tree | 570fbd1ab42d12257a820460fae0e6e7bc891900 /arch/sh/include/cpu-sh4/cpu/dma-sh4a.h | |
parent | 00d6025e58c6e3b229e28cab721c568af5b1ae05 (diff) | |
parent | 58796ce67a80e8725220af83c5a550bf6a4dab12 (diff) | |
download | op-kernel-dev-c1dbccc3c7cc70e8211a7ad6ba55ecbc18e77a5a.zip op-kernel-dev-c1dbccc3c7cc70e8211a7ad6ba55ecbc18e77a5a.tar.gz |
Merge branch 'sh/evt2irq-migration' into sh-latest
Conflicts:
arch/sh/kernel/cpu/sh3/setup-sh770x.c
arch/sh/kernel/cpu/sh3/setup-sh7710.c
arch/sh/kernel/cpu/sh3/setup-sh7720.c
arch/sh/kernel/cpu/sh4/setup-sh7750.c
arch/sh/kernel/cpu/sh4a/setup-sh7343.c
arch/sh/kernel/cpu/sh4a/setup-sh7366.c
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu/dma-sh4a.h')
-rw-r--r-- | arch/sh/include/cpu-sh4/cpu/dma-sh4a.h | 90 |
1 files changed, 46 insertions, 44 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h index 9647e68..f280410 100644 --- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h +++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h @@ -1,75 +1,77 @@ #ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H #define __ASM_SH_CPU_SH4_DMA_SH7780_H +#include <linux/sh_intc.h> + #if defined(CONFIG_CPU_SUBTYPE_SH7343) || \ defined(CONFIG_CPU_SUBTYPE_SH7730) -#define DMTE0_IRQ 48 -#define DMTE4_IRQ 76 -#define DMAE0_IRQ 78 /* DMA Error IRQ*/ +#define DMTE0_IRQ evt2irq(0x800) +#define DMTE4_IRQ evt2irq(0xb80) +#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMARS_BASE0 0xFE009000 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) -#define DMTE0_IRQ 48 -#define DMTE4_IRQ 76 -#define DMAE0_IRQ 78 /* DMA Error IRQ*/ +#define DMTE0_IRQ evt2irq(0x800) +#define DMTE4_IRQ evt2irq(0xb80) +#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMARS_BASE0 0xFE009000 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ defined(CONFIG_CPU_SUBTYPE_SH7764) -#define DMTE0_IRQ 34 -#define DMTE4_IRQ 44 -#define DMAE0_IRQ 38 +#define DMTE0_IRQ evt2irq(0x640) +#define DMTE4_IRQ evt2irq(0x780) +#define DMAE0_IRQ evt2irq(0x6c0) #define SH_DMAC_BASE0 0xFF608020 #define SH_DMARS_BASE0 0xFF609000 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) -#define DMTE0_IRQ 48 /* DMAC0A*/ -#define DMTE4_IRQ 76 /* DMAC0B */ -#define DMTE6_IRQ 40 -#define DMTE8_IRQ 42 /* DMAC1A */ -#define DMTE9_IRQ 43 -#define DMTE10_IRQ 72 /* DMAC1B */ -#define DMTE11_IRQ 73 -#define DMAE0_IRQ 78 /* DMA Error IRQ*/ -#define DMAE1_IRQ 74 /* DMA Error IRQ*/ +#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/ +#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */ +#define DMTE6_IRQ evt2irq(0x700) +#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */ +#define DMTE9_IRQ evt2irq(0x760) +#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */ +#define DMTE11_IRQ evt2irq(0xb20) +#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ +#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMAC_BASE1 0xFDC08020 #define SH_DMARS_BASE0 0xFDC09000 #elif defined(CONFIG_CPU_SUBTYPE_SH7724) -#define DMTE0_IRQ 48 /* DMAC0A*/ -#define DMTE4_IRQ 76 /* DMAC0B */ -#define DMTE6_IRQ 40 -#define DMTE8_IRQ 42 /* DMAC1A */ -#define DMTE9_IRQ 43 -#define DMTE10_IRQ 72 /* DMAC1B */ -#define DMTE11_IRQ 73 -#define DMAE0_IRQ 78 /* DMA Error IRQ*/ -#define DMAE1_IRQ 74 /* DMA Error IRQ*/ +#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/ +#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */ +#define DMTE6_IRQ evt2irq(0x700) +#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */ +#define DMTE9_IRQ evt2irq(0x760) +#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */ +#define DMTE11_IRQ evt2irq(0xb20) +#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ +#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMAC_BASE1 0xFDC08020 #define SH_DMARS_BASE0 0xFE009000 #define SH_DMARS_BASE1 0xFDC09000 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) -#define DMTE0_IRQ 34 -#define DMTE4_IRQ 44 -#define DMTE6_IRQ 46 -#define DMTE8_IRQ 92 -#define DMTE9_IRQ 93 -#define DMTE10_IRQ 94 -#define DMTE11_IRQ 95 -#define DMAE0_IRQ 38 /* DMA Error IRQ */ +#define DMTE0_IRQ evt2irq(0x640) +#define DMTE4_IRQ evt2irq(0x780) +#define DMTE6_IRQ evt2irq(0x7c0) +#define DMTE8_IRQ evt2irq(0xd80) +#define DMTE9_IRQ evt2irq(0xda0) +#define DMTE10_IRQ evt2irq(0xdc0) +#define DMTE11_IRQ evt2irq(0xde0) +#define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */ #define SH_DMAC_BASE0 0xFC808020 #define SH_DMAC_BASE1 0xFC818020 #define SH_DMARS_BASE0 0xFC809000 #else /* SH7785 */ -#define DMTE0_IRQ 33 -#define DMTE4_IRQ 37 -#define DMTE6_IRQ 52 -#define DMTE8_IRQ 54 -#define DMTE9_IRQ 55 -#define DMTE10_IRQ 56 -#define DMTE11_IRQ 57 -#define DMAE0_IRQ 39 /* DMA Error IRQ0 */ -#define DMAE1_IRQ 58 /* DMA Error IRQ1 */ +#define DMTE0_IRQ evt2irq(0x620) +#define DMTE4_IRQ evt2irq(0x6a0) +#define DMTE6_IRQ evt2irq(0x880) +#define DMTE8_IRQ evt2irq(0x8c0) +#define DMTE9_IRQ evt2irq(0x8e0) +#define DMTE10_IRQ evt2irq(0x900) +#define DMTE11_IRQ evt2irq(0x920) +#define DMAE0_IRQ evt2irq(0x6e0) /* DMA Error IRQ0 */ +#define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */ #define SH_DMAC_BASE0 0xFC808020 #define SH_DMAC_BASE1 0xFCC08020 #define SH_DMARS_BASE0 0xFC809000 |