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authorGuennadi Liakhovetski <g.liakhovetski@gmx.de>2010-02-03 14:44:12 +0000
committerPaul Mundt <lethal@linux-sh.org>2010-02-08 09:40:24 +0900
commit623b4ac4bf9e767991c66e29b47dd4b19458fb42 (patch)
tree9cf9c5ef8ac1ab714a35db1baf627fb701a98287 /arch/sh/include/cpu-sh3
parentfc4618575f79eea062cdc51715040e40cd35b71c (diff)
downloadop-kernel-dev-623b4ac4bf9e767991c66e29b47dd4b19458fb42.zip
op-kernel-dev-623b4ac4bf9e767991c66e29b47dd4b19458fb42.tar.gz
sh: fix Transfer Size calculation in both DMA drivers
Both the original arch/sh/drivers/dma/dma-sh.c and the new SH dmaengine drivers do not take into account bits 3:2 of the Transfer Size field in the CHCR register, besides, bit-field defines set bit 2, but the mask only passes bits 1:0 through. TS_16BLK and TS_32BLK macros are bogus too. This patch fixes all these issues for sh7722 and sh7724, other CPUs stay unchanged and might need to be fixed too. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh3')
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dma.h20
1 files changed, 12 insertions, 8 deletions
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
index 0ea15f3..207811a 100644
--- a/arch/sh/include/cpu-sh3/cpu/dma.h
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -20,8 +20,10 @@
#define TS_32 0x00000010
#define TS_128 0x00000018
-#define CHCR_TS_MASK 0x18
-#define CHCR_TS_SHIFT 3
+#define CHCR_TS_LOW_MASK 0x18
+#define CHCR_TS_LOW_SHIFT 3
+#define CHCR_TS_HIGH_MASK 0
+#define CHCR_TS_HIGH_SHIFT 0
#define DMAOR_INIT DMAOR_DME
@@ -36,11 +38,13 @@ enum {
XMIT_SZ_128BIT,
};
-static unsigned int ts_shift[] __maybe_unused = {
- [XMIT_SZ_8BIT] = 0,
- [XMIT_SZ_16BIT] = 1,
- [XMIT_SZ_32BIT] = 2,
- [XMIT_SZ_128BIT] = 4,
-};
+#define TS_SHIFT { \
+ [XMIT_SZ_8BIT] = 0, \
+ [XMIT_SZ_16BIT] = 1, \
+ [XMIT_SZ_32BIT] = 2, \
+ [XMIT_SZ_128BIT] = 4, \
+}
+
+#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
#endif /* __ASM_CPU_SH3_DMA_H */
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