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authorPaul Mundt <lethal@linux-sh.org>2010-09-07 16:12:26 +0900
committerPaul Mundt <lethal@linux-sh.org>2010-09-07 16:12:26 +0900
commit2c5f674339d5e4c02cca7af13ec02bd9b5a96b60 (patch)
tree7327f35f706a9847afaf05a5fd019f7206c534ce /arch/sh/drivers
parent2dbfa1e37dc703631d5421e0b04aecc5a7aff37d (diff)
downloadop-kernel-dev-2c5f674339d5e4c02cca7af13ec02bd9b5a96b60.zip
op-kernel-dev-2c5f674339d5e4c02cca7af13ec02bd9b5a96b60.tar.gz
sh: Establish a SuperHyway<->PCIe window mapping on SH7786 PCIe.
This bumps up the low address to match the physical memory windows for SHway<->PCIe transfers. The previous implementation was banking on a 1:1 virt<->phys SHway mapping, which doesn't apply here. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers')
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 40b0ed0..4cd8314 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -354,8 +354,8 @@ static int pcie_init(struct sh7786_pcie_port *port)
__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
chan->reg_base + SH4A_PCIEPAMR(i));
+ pci_write_reg(chan, res->start, SH4A_PCIEPARL(i));
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
- pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i));
enable_mask = MASK_PARE;
if (res->flags & IORESOURCE_IO)
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