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| author | Paul Mundt <lethal@linux-sh.org> | 2010-02-01 20:01:50 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-02-01 20:01:50 +0900 |
| commit | b6c58b1d987a5795086c5c2babd8c7367d2fdb8c (patch) | |
| tree | 3ec992af50f44dd09ff125165ea1c4ef41b2aecc /arch/sh/drivers/pci/pci-sh7780.h | |
| parent | ef407beefbd9928792ccc93857e408e0057bc17b (diff) | |
| download | op-kernel-dev-b6c58b1d987a5795086c5c2babd8c7367d2fdb8c.zip op-kernel-dev-b6c58b1d987a5795086c5c2babd8c7367d2fdb8c.tar.gz | |
sh: Improved multi-resource handling for SH7780 PCI.
The SH7780 PCI controller supports 3 different ranges of PCI memory in
addition to its PCI I/O window. In the case of 29-bit mode, only 2 memory
windows are supported, while in 32-bit mode all 3 are visible. This
attempts to make the resource handling completely dynamic and to permit
platforms to map in as many apertures as they can handle.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/pci-sh7780.h')
| -rw-r--r-- | arch/sh/drivers/pci/pci-sh7780.h | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h index dee069c..205dcbe 100644 --- a/arch/sh/drivers/pci/pci-sh7780.h +++ b/arch/sh/drivers/pci/pci-sh7780.h @@ -26,12 +26,6 @@ #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */ -#define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */ -#define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ - -#define SH7780_PCI_IO_BASE 0xFE200000 /* IO space base address */ -#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */ - #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ /* SH7780 PCI Config Registers */ @@ -46,12 +40,8 @@ #define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */ #define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */ -#define SH7780_PCIMBR0 0x1E0 -#define SH7780_PCIMBMR0 0x1E4 -#define SH7780_PCIMBR1 0x1E8 -#define SH7780_PCIMBMR1 0x1EC -#define SH7780_PCIMBR2 0x1F0 -#define SH7780_PCIMBMR2 0x1F4 +#define SH7780_PCIMBR(x) (0x1E0 + ((x) * 8)) +#define SH7780_PCIMBMR(x) (0x1E4 + ((x) * 8)) #define SH7780_PCIIOBR 0x1F8 #define SH7780_PCIIOBMR 0x1FC #define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */ |
