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| author | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2013-10-28 14:48:30 +0100 |
|---|---|---|
| committer | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2013-11-04 13:51:47 +0100 |
| commit | 106078641f32a6a10d9759f809f809725695cb09 (patch) | |
| tree | a65201fd31994348a067c63e820530ad15387476 /arch/s390/include/asm/processor.h | |
| parent | be39f1968e33ca641af120a2d659421ad2225dea (diff) | |
| download | op-kernel-dev-106078641f32a6a10d9759f809f809725695cb09.zip op-kernel-dev-106078641f32a6a10d9759f809f809725695cb09.tar.gz | |
s390/mm,tlb: correct tlb flush on page table upgrade
The IDTE instruction used to flush TLB entries for a specific address
space uses the address-space-control element (ASCE) to identify
affected TLB entries. The upgrade of a page table adds a new top
level page table which changes the ASCE. The TLB entries associated
with the old ASCE need to be flushed and the ASCE for the address space
needs to be replaced synchronously on all CPUs which currently use it.
The concept of a lazy ASCE update with an exception handler is broken.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'arch/s390/include/asm/processor.h')
| -rw-r--r-- | arch/s390/include/asm/processor.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h index a56e634..0a876bc 100644 --- a/arch/s390/include/asm/processor.h +++ b/arch/s390/include/asm/processor.h @@ -144,9 +144,7 @@ struct stack_frame { regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ regs->gprs[15] = new_stackp; \ - __tlb_flush_mm(current->mm); \ crst_table_downgrade(current->mm, 1UL << 31); \ - update_mm(current->mm, current); \ execve_tail(); \ } while (0) |
