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| author | Palmer Dabbelt <palmer@sifive.com> | 2018-03-07 15:57:28 -0800 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-03-14 21:46:29 +0100 |
| commit | cc6c98485f8e61fb3d6c51821fc75384e5a3a9c3 (patch) | |
| tree | e3cb0f7eadebc546f65b7eebde84d48b7c7b77d6 /arch/riscv/Kconfig | |
| parent | caacdbf4aa567ab5e8de1a4070195c5d3e8f1340 (diff) | |
| download | op-kernel-dev-cc6c98485f8e61fb3d6c51821fc75384e5a3a9c3.zip op-kernel-dev-cc6c98485f8e61fb3d6c51821fc75384e5a3a9c3.tar.gz | |
RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler
The existing mechanism for handling IRQs on RISC-V is pretty ugly: the irq
entry code selects the handler via Kconfig dependencies.
Use the new generic IRQ handling infastructure, which allows boot time
registration of the low level entry handler.
This does add an additional load to the interrupt latency, but there's a
lot of tuning left to be done there on RISC-V so it's OK for now.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Acked-by: Stafford Horne <shorne@gmail.com>
Cc: jonas@southpole.se
Cc: catalin.marinas@arm.com
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux@armlinux.org.uk
Cc: stefan.kristiansson@saunalahti.fi
Cc: openrisc@lists.librecores.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lkml.kernel.org/r/20180307235731.22627-3-palmer@sifive.com
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 04807c7..148865d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -33,6 +33,7 @@ config RISCV select MODULES_USE_ELF_RELA if MODULES select THREAD_INFO_IN_TASK select RISCV_TIMER + select GENERIC_IRQ_MULTI_HANDLER config MMU def_bool y |
