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| author | Roland Dreier <rolandd@cisco.com> | 2005-11-07 00:58:11 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-11-07 07:53:26 -0800 |
| commit | fcc188e7fdddd8b23f900e485e6b3db05e7375f4 (patch) | |
| tree | 8da8cac96f2ca884039e31cd6ff9d00e21cc2aea /arch/ppc | |
| parent | 2104da90a9aeef31ff6441d171a7d0492088f1d0 (diff) | |
| download | op-kernel-dev-fcc188e7fdddd8b23f900e485e6b3db05e7375f4.zip op-kernel-dev-fcc188e7fdddd8b23f900e485e6b3db05e7375f4.tar.gz | |
[PATCH] ppc32: Allow ERPN for early serial to depend on CPU type
The PowerPC 440SPe supports up to 16 GB of RAM, and therefore its IO registers
are at 0x4_xxxx_xxxx instead of being at 0x1_xxxx_xxxx like most other PPC 440
chips. To allow for this, this patch moves the definition of the ERPN used
for mapping UART0 from being hard-coded in the head_44x.S assembly code to
being defined in ibm44x.h.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc')
| -rw-r--r-- | arch/ppc/kernel/head_44x.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S index 8b49679..677c571 100644 --- a/arch/ppc/kernel/head_44x.S +++ b/arch/ppc/kernel/head_44x.S @@ -190,8 +190,8 @@ skpinv: addi r4,r4,1 /* Increment */ /* xlat fields */ lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */ -#ifndef CONFIG_440EP - ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */ +#ifdef UART0_PHYS_ERPN + ori r4,r4,UART0_PHYS_ERPN /* Add ERPN if above 4GB */ #endif /* attrib fields */ |
